16 ms·

Chip design shifts as fundamental laws run out of steam

229 points by _hypx 4y ago

geenew 4y ago
This graph in the article is pretty fascinating: https://i0.wp.com/semiengineering.com/wp-content/uploads/Picture1-2.png https://i0.wp.com/semiengineering.com/wp-content/uploads/Pic... (not really a png, apparently, but a webp file)
- Traubenfuchs 4y ago
  More depressing -number of cores will also level off eventually and where does that leave us then? Will we actually have to optimize our code instead of pushing each hello world request through hundreds of function calls? I also assume some niches are actually already 90%+ optimized. Once the cores level off it‘s stagnation here too.
  - deleted 4y ago
    [deleted]
  - joe_the_user 4y ago
    Would the number of cores in a GPU level off? It seems like intensive computing of all sort will migrate to gpgpu programming.
    - Traubenfuchs 4y ago
      Shrinking has almost stopped too and you can only make a chip that big before it runs into other constraints.
      - singularity2001 4y ago
        There is a lot of room for development before the exponential curve can be carried by the next paradigm: at least for desktop computers we are still decades away from case filling 3D "compute cubes".
        brazzy 4y ago
        It's quite possible that kind of thing has hard limits set by cooling.
        singularity2001 4y ago
        sure but usually before hard limits are reached a new paradigm is ready to take over
      - plasticchris 4y ago
        The wafer scale computing folks would disagree...
        Traubenfuchs 4y ago
        This is insane. https://www.eetimes.com/powering-and-cooling-a-wafer-scale-die/ https://www.eetimes.com/powering-and-cooling-a-wafer-scale-d...
    - ummonk 4y ago
      Seems like the latest Nvidia GPUs aren't really an improvement over the previous ones, but just bigger and proportionally more expensive. So maybe the leveling off in performance is already starting to happen.
      - brokenmachine 4y ago
        That is not true. The 4090 uses less power than a 3080ti while being 63% faster. https://www.techpowerup.com/review/nvidia-geforce-rtx-4090-founders-edition/39.html https://www.techpowerup.com/review/nvidia-geforce-rtx-4090-f... , and 45% better performance than a 3090ti while using 2% less power (at 4k). https://www.techpowerup.com/review/nvidia-geforce-rtx-4090-founders-edition/32.html https://www.techpowerup.com/review/nvidia-geforce-rtx-4090-f... Can't find the link now, but I saw a youtube video where they did an analysis of it at different wattage limits and it performed very nicely. 4090 draws a lot of power, but Nvidia has just chosen to work at the diminishing returns end of the curve. It's a halo product for people who will pay for the top of the range. I mean, look at the price!
  - mschuster91 4y ago
    I'd guess we get more hardware acceleration. In classic computers (PCs, laptops, servers), for stuff like audio/video codecs, that's been available for decades, but I'd say the next big push will be ethernet/wifi accelerators that do stuff like checksum calculation/verification, VLAN tagging or even protocol-level stuff like TLS in the chip itself - currently, that's all gated for expensive cards [1], I'd expect that stuff to become mainstream over the next few years. Another big part will be acceleration for disk-to-card data transfer [2] - at the moment, data is being shifted from the disk to RAM to GPU/other compute card. Allowing disks to interface with compute cards will be a lot of work - basically, there needs to be a parallel filesystem reader implementation on the disk itself, on the DMA controller or in the GPU, which is a lot of effort to get done right with most modern and complex filesystems - but in anything requiring high performance removing the CPU bottleneck should be well worth the effort. Mobile is going to be more interesting because of power, space and thermal constraints and a lot of optimization already being done because unlike on classic computers vendors couldn't just go and use brute force to get better performance, and there is a bit of an upper cap on chip/package size as well. Probably we'll see even more consolidation towards larger SoCs that also do all the radio communication stuff if not on the same chip then at least in the same package, so the end game there is one single package that does everything and all that's needed on the board are RF amplifiers and power management. All the radio stuff will move to SDR sooner or later, allowing for far faster adoption of higher bandwidth links and with it, a reduce in power consumption as the power-expensive RF parts have to be powered on for less time to deliver the same amount of data. [1] https://docs.nvidia.com/networking/display/FREEBSDv370/Kernel+Transport+Layer+Security+%28kTLS%29+Offloads https://docs.nvidia.com/networking/display/FREEBSDv370/Kerne... [2] https://developer.nvidia.com/blog/gpudirect-storage/ https://developer.nvidia.com/blog/gpudirect-storage/
    - rjsw 4y ago
      Network offload has been available in low-cost controllers for a long time, TLS isn't common though. It could be better if network controllers just had a documented local CPU, then the firmware could be extended over time to add new features.
  - JohnJamesRambo 4y ago
    What if aliens show up and they are thousands of years ahead of us and they don’t have anything much more powerful than an i9 running their UFO?
    - ars 4y ago
      Then that pretty much spells the end of true AI. We may shift to computers that operate off of chemical signals instead of electrical ones - like the brain.
    - bee_rider 4y ago
      Who knows what sort of tech aliens would have? I don't think this whole foray into general purpose computing was necessarily pre-destined. Maybe their whole system could look more like a bunch of strung-together ASICs. "You made your computers drastically less efficient so that anyone could program them? Why would you want your soldier-forms and worker-forms to program computers? Just have the engineer-forms place the transistors correctly in the first place, duh."
      - rl3 4y ago
        >Who knows what sort of tech aliens would have? I don't think this whole foray into general purpose computing was necessarily pre-destined. It's sometimes fun to think that technology is a function of the intelligence that creates it. What if the aliens have some vastly different perception of reality than us? Things we consider obvious to them may not be, and vice versa. The underlying desires and motivation different. Humans for example, often tend to invent things for the sake of it. Imagine a species that doesn't do that. Or an organic FTL drive conjured into existence over eons via distributed intelligence. Weird.
        checkyoursudo 4y ago
        > Or an organic FTL drive conjured into existence over eons via distributed intelligence. Weird. E.g., What if the first aliens to find us are hyperintelligent slime molds, whose entire existence is predicated on finding the shortest distance between two points in higher-dimensional space and then traveling there to see what there is to eat?
  - pbazarnik 4y ago
    The "cores" are becoming more specialized and optimized for domain specific tasks. Compiler technology advancements are needed to take advantage of such heterogenous architectures in a transparent way. LLVM MLIR started that already.[1,2] The alternative is being stuck with each silicon vendor's proprietary solutions like CUDA. [1] https://mlir.llvm.org/ https://mlir.llvm.org/ [2] https://www.theregister.com/2022/04/04/compiling_the_future/ https://www.theregister.com/2022/04/04/compiling_the_future/
  - tyingq 4y ago
    There's also ideas like the Mill processor. Though it's hard to avoid comparisons to Itanium, and how a mountain of money still didn't produce a compiler that could unlock what initially sounded like a better ecosystem.
  - Frost1x 4y ago
    >More depressing -number of cores will also level off eventually and where does that leave us then? Short of breakthroughs (e.g. quantum and currently unknowns), the only clear path is less generalized architectures and more specialized chips. As you move more towards ASICs from general architectures you get improved performance, reduced power, and so on. We've lived in the era of software where hardware was abundant and cheaper than an engineers time. Throw more hardware at it and make sure you have generally optimal algorithms in most your run paths. That's going to change more and more and I suspect we're going to have to start rethinking or redeveloping some layers of abstraction between current software and hardware. As it stands now we're building more and more complex things atop weaker intermediary layers of abstraction to save time and meet budgets but that's going to have to be revisited in the future and the inefficiency debts we've been building up will need to be paid down. Clear code will become less of a top priority when clever optimizations can be added in that may not be so clear. We're still many many year away from this but that's my prediction.
    - urthor 4y ago
      Not necessarily a problematic trend. It takes thousands and thousands of engineers to produce a general purpose chip. It takes... one smart lady to optimize a widely used library for FPGA acceleration.
  - duped 4y ago
    The metric is performance per watt per dollar. At the moment the fact is that the amount of compute available per watt dollar is ridiculously cheap, crypto not withstanding. We are not limited by compute resources but by business practices. The organizational cost of software design is where the next gains are, not technological.
  - stn_za 4y ago
    Can't wait. People should be so ashamed that what's basically an IRC client (Slack) requires more than 4GB of ram and so many cores. Laziness. Truly.
- MereInterest 4y ago
  Back in grad school, one of the analysis programs I used dated back to the mid 70s. The original paper gave a performance metric for a test program, which I compared to the runtime on a Chromebook running Linux. I was curious how closely that scaled with Moore's Law, and computed "initial_release + (1.5 years)*log2(initial_runtime/current_runtime)". That is, assuming that the change in program speed has increased due to hardware improvements, and those hardware improvements follow Dennard scaling, what year is it? This (admittedly very rough) measurement ended up giving 2003. It was wrong by over a decade from the actual date, but correctly gave the date at which clock frequencies stopped improving.
- nullifidian 4y ago
  Not sure if it's exactly accurate with the plateauing trend -- single-threaded performance almost doubled in the last 5 years.
  - pclmulqdq 4y ago
    It's a log scale graph, it shows a doubling. The performance just isn't increasing as fast as it was before.
    - hansel_der 4y ago
      yea, buying a pc in the early intel era was a somewhat double edgded sword because you knew that the next generation would come out in a year or so and it would probably have more than double the performance.
      - Nomentatus 4y ago
        For many years my friends and I had a rule that we wouldn't buy a new computer until it offered at least 4X the speed of our old one. We didn't have to wait all that long.
- mrandish 4y ago
  My entire career in computers spans the 40 years in that graph. The constant leaps in fundamental speed were exhilarating and kind of addictive for technologists like myself. As the rate of progress has fallen off over the past decade it's been sad to see the end of an era. I'm sure speeds and capabilities will continue to increase, albeit much more gradually, but significant gains are going to come slower, harder and at greater cost. The burden will have to be shouldered by system architects and programmers in finding clever ways to squeeze out net gains under increasingly severe fundamental constraints (density, leakage, thermals, etc). Back when I started programming as a teen in 1980 with 4k of RAM and ~1 Mhz 8-bit CPUs, knowledge of the hardware underneath the code and low-level assembly language skills were highly valuable. Over the years, the ability to think in instruction cycles and register addressing modes grew anachronistically quaint. Now I suspect those kinds of specialized 'down-to-the-metal' optimization skills may see a resurgence in value.
  - zaptrem 4y ago
    This graph shows transistors basically maintaining pace and completely disregards multi-core performance. Of course single core perf will rise more slowly when a chip now has 8-64x as many cores.
    - StillBored 4y ago
      Which is great if you have a traditional server application servicing a lot of independent requests, or giant linear equations that can be solved in parallel. OTOH, the graph has an amadal's law section, which for many tasks is pretty out of steam (aka desktop web browsing/javascript JIT/etc). I'm not going to be so stupid as to say 8 cores should be enough for anyone (while attached to a machine with 128) but you have to wonder if the stable diffusion style apps running on your desktop are going to be mainstream, or isolated to the few who choose to _need_ them as a hobby or a smaller part of the public that uses them for commercial success. AKA, I can utilize just about every core i'm given with parallel compiles, or rendering a 4K video, but I'm pretty sure i'm the only one in my immediate family that needs that. My wife in the past might have done some simulation work, but these days the heaviest thing she runs on her PC is office products. This really gets back at the Arm big.little thing, where you really want 99% of your application usage to run on the big cores. The little cores only exist for background/latency insensitive tasks, and the odd case where the problem actually can utilize a large number of parallel cores and needs to maximize efficiency in the power envelope to maximize computation. AKA throw a lot of lower power transistors at the people rendering video/etc, and leave them powered off most of the time. AKA, put another way, the common use case is a few big powerful cores for normal use, playing games, whatever with one or two high efficiency processors for everything else and a pile of dark silicon for the rare application that actually can utilize dozens of cores because its trivial to parallelize and doesn't work better being offloaded to a GPU. I suspect long term intel was probably right with larrabee, they were just a decade or two early. So, economically I don't see people buying machines with a couple hundred cores that sit dark most of the time. Which will drive the price up even more, and make them less popular.
- causi 4y ago
  This trend of browsers to increasingly lie to me about what I'm looking at is infuriating.
  - modeless 4y ago
    The URL is a lie but that's not the browser's fault. It's correctly showing you the URL that you requested and the server responded to. If you save the file locally the browser will give it the correct extension.
  - q-big 4y ago
    > This trend of browsers to increasingly lie to me about what I'm looking at is infuriating. The browser does not lie to you, it just does not show the MIME type of the content. I do agree that it would make sense that the browser shows the MIME type of the content that is currently displayed, but this is opposition to the current fashion (in particular pioneered by Apple) of "simplifying" everything.
    - deathanatos 4y ago
      > The browser does not lie to you, it just does not show the MIME type of the content. In this particular case, Firefox does: > Picture1-2.png (WEBP Image, 1054 × 593 pixels) is the title on the tab. (The ".png" comes from the URL, as a sibling notes.) Chrome does not.
- deleted 4y ago
  [deleted]
- samstave 4y ago
  where the heck is Transmeta ??? intel was so afraid of them in 1997 Obv AMD was the true and once... but there was a lot of Transmeta-fear back then too
  - jecel 4y ago
    Transmeta announced their first product, the Crusoe processor, in 2000. Before then they were highly secretive and nobody knew what area they would compete in. Intel was indeed worried about the laptop market when the Crusoe came out, but quickly adopted the voltage and frequency scaling into their own processors negating some of Transmeta's key technical advantages. Meanwhile, IBM changed directions as a third party fab (they dropped bulk CMOS to focus on SiliconOnInsulator) leaving Transmeta without a product to sell until they could find a new fab and design their next generation product for that.
- amelius 4y ago
  How is it that the number of transistors still grows exponentially, while the power use has plateaued?
  - deleted 4y ago
    [deleted]
  - eru 4y ago
    Each transistor uses less power?
    - amelius 4y ago
      Exponentially less.
  - Swenrekcah 4y ago
    I think I can say the following. Smaller transistors mean fewer electrons that go in and out every clock cycle, so less power per transistor. Higher clock frequency means more cycles per second, that is more electrons spent per second thus higher power consumption. Since clock frequency has stabilised and the total area of a chip is I think not much larger than before, it is expected to see the power consumption stabilising. I also believe I read somewhere that one of the reasons clock frequency stoped increasing was that the power consumption became too high for the chips to handle the thermal dissipation.
- joshspankit 4y ago
  I wonder how much of that flattening is because chips are now hovering just under the 5GHz/6Ghz wifi frequencies. Yes we have techniques that help them avoid each other, but it seems like it would be enough of a tech and PR hassle that companies wouldn’t bother.
  - hansel_der 4y ago
    pretty sure it has something to do with speed of light divided by clock speed
    - kloch 4y ago
      Pretty sure it has everything to do with heat dissipation
      - hansel_der 4y ago
        probably true as well. also iirc the actual clock of the logic gates is a factor above the 'operations clock'
    - joshspankit 4y ago
      I hadn’t even considered that there is a physical limitation. I’m too lazy to look it up now, but when I first read this I feel like the math said electrons can move at maximum 5cm in a single 5GHz clock cycle? That’s wild.
      - hansel_der 4y ago
        the eletrons do not have to 'move' the entire way for transfer of information because they will push the already present ones further.
        joshspankit 4y ago
        Well yes, but that’s an academic difference unless you’re stating that they can transfer information faster than light.
- jdthedisciple 4y ago
  interesting, so basically since 2010 no all-to-significant progress has really been made despite the scaling in logical processor count. This is considering the vast majority of software basically still uses only a single core
  - dspillett 4y ago
    > the vast majority of software basically still uses only a single core And that which does use multiple cores, sometimes only scales well to a few because then other bottlenecks† start to become most significant. Many things are not so “embarrassingly parallelisable” that they can easily take full advantage of the power available from expanding the number of processing units available beyond a certain point. -- [†] things no longer being “friendly” to the amount or arrangement of shared L2/L3 cache as the amount of threads grow causing more cache-thrashing, hitting other memory bandwidth issues, or for really large data you might be considering issues as far down as the IO subsystem or network.
- andy_ppp 4y ago
  I’d love to see how GPUs fit into this picture; are we getting more transistors on a die but designs are not getting much faster?
- abbeyj 4y ago
  You might like https://github.com/karlrupp/microprocessor-trend-data https://github.com/karlrupp/microprocessor-trend-data
shadowgovt 4y ago
I wonder how long until software will also need to shift. The hardware can only become so parallel before the software will have to change to more closely match its reality.
- hinkley 4y ago
  I think there’s a potential for collaboration between borrow checkers and more aggressively NUMA architectures, but the problem is you still have to run commercial operating systems on any chips you make. That’s less of a problem for embedded systems and controllers, but then you lose a lot of the value as well.
- IshKebab 4y ago
  That was one of the few good parts of this article. Software will have to become power-aware. You already see that on phones where software has to schedule tasks with the OS rather than running them whenever it wants.
cudgy 4y ago
For consumer use and probably many commercial uses too, I am becoming skeptical about hardware performance improvements and whether users are gaining sufficient benefits from these improvements. Software has become so wasteful of resources that the hardware improvements are offset and there is little perceptible improvement for the end user. This is of course not the fault of the chip makers, but the fault of the movement to inefficient web apps and more resource intensive languages and frameworks.
- jiggawatts 4y ago
  I find myself agreeing with Jim Keller. His stance — from very high up in the chip design industry — is that individual teams at the bottom may be seeing the end of the road, but there are alternate paths being explored by other teams. Often these alternate paths aren’t yet commercialised — mere options — but enable the overall improvements to keep going without getting stuck. Some examples: Stacking and joining chiplets will soon enable over 2 TB/s memory bandwidths for ordinary devices, far higher than the 50 GB/s typical of mid-tier DIMM memory. Storage latency and IOPS is still going up. Millions of random accesses per second with ~20 microsecond latencies enabled technologies like DirectX DirectStorage. This totally changes the way game engines work and how their art assets are authored. I could go on…
snvzz 4y ago
RISC-V has been engineered to support this very shift. It can thus be the base ISA for all these accelerators to be built on.
- Taniwha 4y ago
  I'm a RISC-V designer, I'm afraid it's not a magic bullet for these sorts of issues. What it does do is free lots of designers to work on solutions and build off of each other's work
vinyl7 4y ago
I look forward to Moore's law ending, because then software might actually become good again (lol probably not)
- FPGAhacker 4y ago
  No kidding, almost 30 years later and windows still finds a way to make my work computer run like crap. Looking at a flame graph 60 levels deep demonstrates the problem pretty well I think.
- iveqy 4y ago
  Software seems like a very immature field where we can still do a lot to increase performance. I'm looking forward to the shift
  - vinyl7 4y ago
    Software has become more immature over the last decades because developers lost the engineering mindset and skills to write optimized software like they could back in the days where we only had a couple of MB of ram. It really does not require new expertise or tech at all to cut latency and load times by 90%. Programmers have to get back to being engineers instead of just duct taping libraries together or praying that the dumb GC knows what its doing
    - hajile 4y ago
      Are customers willing to pay 10x the cost for the mildly better experience? At most places, there’s barely enough time to implement things completely let alone to optimize everything properly. It’s also noteworthy that optimizing 10kloc from yesteryear is a much easier task than optimizing a few mloc of code today. We didn’t just lose all those optimized libraries. The requirements bloated and nobody wants to reduce features.
      - vinyl7 4y ago
        I would argue that the only reason we went from 10kloc to +1mloc is because of the proliferation of bad coding practices...like OOP
sp332 4y ago
Moore's law is not a fundamental law, it's just an observation. Amdahl's law is holding just as well as ever.
- amirhirsch 4y ago
  Amdahl’s law is also just a conjecture unless you have a proof that P is disjoint from NC
kayson 4y ago
The article doesn't really mention one of the biggest problems: cost. These new process nodes are insanely expensive. Far moreso than before. This is one of the biggest drivers of new packaging technologies (chiplets). Companies simply can't afford to manufacture their entire design on the latest process. There are even still newer transistor designs that promise further improved performance but will be even more cost prohibitive. I'm not convinced that there are any hard EDA problems here, despite the fact that EDA as an industry in general is woefully archaic, especially when compared to the equivalent in the software world. We've been doing multi-layer and/or multi-die packages for a long time. It's more of a project management challenge, having to get different teams (process, packaging, design, verification) to work together earlier on in the design cycle, and more frequently throughout.
- conjecTech 4y ago
  Chiplets aren't so much driven by a need for heterogenous processes as much as minimizing the yield impact of defects. Ian Cutress has a good portion covering it in this recent video: https://www.youtube.com/watch?v=oMcsW-myRCU https://www.youtube.com/watch?v=oMcsW-myRCU. In short, if your process produces 20 defects per wafer, and you can fit 100 chip on a wafer, you're going to end up with ~84% yield(ie, slightly less than 20% loss). If you are able to split that same chip into 2 equal-sized pieces and make twice as many, your yield is now above 90%. AMD has also made them composable in such a way that they have to produce and stock far fewer ICs to fulfill all of their SKUs, which is also another fantastic benefit.
  - kayson 4y ago
    Absolutely. Yield is obviously a big part of cost-per-die, but it's not just defect density related. When a node is first released, the process is not as well controlled so you end up with yield loss because the process doesn't match the models (in the extremes) and dies fail at various testing stages. This obviously gets better over time, but it's still a major issue for companies designing in the latest technologies. Anecdotally I'd say there's a ~3X reduction in the "sigma" of the process over 3-5yrs. Of course these issues have always existed, but wafer costs have never been so high, and yields never so low (both because of increased defect density and worse process control with new transistors).
travisgriggs 4y ago
If we start shifting towards specialized hardware configurations to solve specialized problems, how does “move everything to the cloud communicating through fragmented docker images” fit? It just seems weird to me to see posts of spending lots of money on complicated scalable Kubernetes clusters, but at the same time people are putting their AI computation engines right on die so that they get good cache coherence. Maybe they’re more resolvable than it seems.
- c54 4y ago
  K8s GPU nodes are already kind of an example of this-- the app can still access the specialty capabilities of the hardware, we just have to make sure to tell the scheduler "hey run this app on this kind of node with this flavor of capabilities". I could imagine that kind of flavor capability growing and becoming more fleshed out Except k8s calls it 'taints' which is uh a weird choice.
  - kevincox 4y ago
    Taints is a funny name when you look at it like that but taints are actually the opposite half of the story. If you want a Pod to be scheduled with a certain node you need to add affinity. The taints are to ensure that your average nginx pod doesn't run on the specialty hardware and block the pods that actually need it. In theory the scheduler could be smart enough to evict the pods that don't need the special node but IDK if the kube scheduler is smart enough. Even then it may he preferable to have the taint though to reduce the eviction rate.
- bippingchip 4y ago
  This is probably one of the biggest challenges ahead, likely more so than making hardware that still somehow scales despite Moore’s law slowing down and tapering out entirely. The increased scale of integration with advanced 3D packaging and chiplets is a nice way forward, but the heterogeneity of those solutions need innovation at the programming model as much as anything else: how do you make such a complex system accessible in a way that the programmer can actually use it efficiently? As much as I like semiengineering and their articles, they are very hardware and process technology focused and tend to miss the software side of things.
lumost 4y ago
I wonder if part of the recent switch back to statically typed languages is merely a reflection of changing compute requirements. During my career, single core performance has only doubled at best. Scale out has worked… but it hasn’t been cheap.
- grumpyprole 4y ago
  Or perhaps because knowing/reasoning about at least some properties before running a program is a good thing? Optimisation is only one consequence of static types. Perhaps the reason is that static type systems are getting better and less intrusive.
prng2021 4y ago
I love buying new and better gadgets like everyone else but if cpu advancements froze after the next generation of ones using the 3nm transistor node, would life on Earth really be that bad? We’d be in a world where we have no choice but to optimize existing algorithms, software, and hardware designs. And yes, after many years even that would reach its limits. Even so, I still think life would be great for every generation that lives on after that.
- FrontierPsych 4y ago
  It really makes no difference to most people. I have 10 and 15 year old computers and they work just fine for me. Web browsing, spreadsheets, word processing documents. I don't use the latest gamer stuff, or have 285-dimensional graphics that rotate in 48 dimensions or whatever. I'd think that 95% of the computer users are just like me. Pissed me off...my parents essentially use their computer and smart phones the same exact way - email,browse the web, and that's about it. My siblings decided they had to upgrade and got them new computers and smartphones. WTF? Total waste of maybe $5000. If anyone else has $5000 that they want to spend on nothing, let me know and I will give you my bank routing number and account number and you can just send it to me for nothing in return, too. :P
- 1123581321 4y ago
  I would personally be content, but I’m thankful for the advances made possible by faster computing, especially in medicine, and I’d like to see more. If we keep advancing computing power, today’s research supercomputers will be tomorrow’s personal computers in the hands of researchers of all income levels all over the world.
  - jiggawatts 4y ago
    The vast majority of hardware devices haven’t even caught up to 14nm, let alone 3nm which is still an experimental node used by a few customers “at risk”. It would take decades at the current pace of progress just for everyone to catch up to the current bleeding edge. I would have retired from IT work by the time that happens! In other words, we’re already at the stage that many people will continue to see non-stop improvements even if 3nm is “the end”. Meanwhile Intel says that their 18A node is looking good and ahead of schedule…
lob_it 4y ago
Dating back to the turn of the century, I can still recall the pleasure of building my 1st of many SMP desktops/workstations with an Abit VP6 to game on and work on at home. In 2022, I would almost expect to see mobo designers and chip manufacturers start rolling out deca-socket designs for compute and automotive use, giving users (okay.. Just the nerds and geeks) the option of mixing-and-matching chips to accomodate custom configurations (and unthought of use cases). The CPU wall almost reminds me of automotive where the engines may be hitting cooling/fuel system limits of the current technologies, but still has plenty of optimizations available for unsprung weight, torsional rigidity, coefficient of drag and so on. It may not address the power efficiency angles, but for many users, having 10 sockets to add optimized compute chips (main cpus, AI accelerators, graphics enhancement chips and a number of other feature-enhanced chips) keeps the R&D money flowing until the industry gets over this next hurdle (they always do). The author states that the expense of pushing moores law, etc is becoming cost prohibitive, so take a break and rock some modern PCB designs.
- davidgay 4y ago
  > In 2022, I would almost expect to see mobo designers and chip manufacturers start rolling out deca-socket designs for compute and automotive use It's called the PCIe bus. And before you say "but it doesn't meet my needs / it's latency is too high / it's bandwidth is too low", come up with some ideas on how to do that better rather than just say "add sockets".
  - lob_it 4y ago
    I rocked a Commodore 128.. Don't F with me :p Power is nothing without spittle (I'm sure at least one person said it) I'm not familiar with the lingo, but I was thinking of multilayer sockets, with a higher bandwidth loop/ring for the primary sockets with the PCIe coming off the CPUs in a traditional fashion. Perhaps I read about that with the opterons ages ago.
    - davidgay 4y ago
      86=lda a (which I still remember), is all I have to say.
stopdropnhotpot 4y ago
They're still predicting shift away from silicon is another 5 years out. No, really. It's been 20 years+ at this point they've been developing alternatives and they can make chips but they're far from being competitive with silicon in any metric. It's called single crystal complex oxide or SiC
DeathArrow 4y ago
Can't we move over from silicon? I've read about countless tries to design CPUs based on different principles and materials like carbon, optical and even biological modeled systems. So far our best results still come from trying to shrink silicon transistors.
- prox 4y ago
  With so much invested in Silicon it is hard to boot up a whole new paradigm. In that sense working with Silicon is much easier / less friction relatively speaking.
  - jiggawatts 4y ago
    I hear that the plan is (roughly) to try and grow thin layers of something like silicon carbide (SiC) on top of silicon wafers.
- easygenes 4y ago
  The current long-term roadmaps put a rough target of 2036 for this to be practical. [1] 1: https://youtu.be/TwgvJSOa09M?t=495
DeathArrow 4y ago
If power, heat and efficiency are valid concerns, we might as well try to optimize the software, use less abstractions, go for the code that use the least CPU cycles, use less interpreted languages, more AOT compiled ones.
- TaylorAlexander 4y ago
  In general, sure, for things like web pages etc. In fields like robotics people are always desperately trying to improve the efficiency of their algorithms but it really seems like we just need way more powerful silicon.
bullen 4y ago
What they are doing now is trying to separate power and data, so that they approach the die from different sides. But the memory bottleneck cannot be solved so we are stuck with the CPU performance per watt we have had since Ivy Bridge around 2012. DRR3 has lower latency than DDR4,5,6+ GPU is also stuck. The ONLY solution is to code vanilla Java (no/few external deps.) on the server and mostly C with ++ compiler on the client. Forget Rust, Go, WASM, etc.
- bheadmaster 4y ago
  > The ONLY solution is to code vanilla Java (no/few external deps.) on the server and mostly C with ++ compiler on the client. > Forget Rust, Go, WASM, etc. Why?
  - bullen 4y ago
    Because you need a VM with GC on the server so it doesn't crash and can share memory between cores properly. On the client you can go lower since deploying new buggy code only affects some of the clients and not the entire server (unless you deploy completely untested patches). - Rust seg. faults. - Go has no VM - WASM has no GC.
    - bheadmaster 4y ago
      How exactly are GC and VM crucial to "not crashing" and "sharing memory"? And what exactly do you mean by "not crashing"? Crashing is a broad term, and I assume you mean C++-style-crash-because-of-type-safety-errors. Go does not run on VM, yet is type safe. Rust can indeed cause segfaults, but that's only if you (ab)use the "unsafe" mechanism, which is explicitly labeled as not safe. As long as you stick to the safe Rust, segfaults are impossible. Could you explain your reasoning to me in a little more detail, please?
      - bullen 4y ago
        "While I'm on the topic of concurrency I should mention my far too brief chat with Doug Lea. He commented that multi-threaded Java these days far outperforms C, due to the memory management and a garbage collector. If I recall correctly he said "only 12 times faster than C means you haven't started optimizing"." - Martin Fowler https://martinfowler.com/bliki/OOPSLA2005.html https://martinfowler.com/bliki/OOPSLA2005.html "Many lock-free structures offer atomic-free read paths, notably concurrent containers in garbage collected languages, such as ConcurrentHashMap in Java. Languages without garbage collection have fewer straightforward options, mostly because safe memory reclamation is a hard problem..." - Travis Downs https://travisdowns.github.io/blog/2020/07/06/concurrency-costs.html https://travisdowns.github.io/blog/2020/07/06/concurrency-co... "Inspired by the apparent success of Java's new memory model, many of the same people set out to define a similar memory model for C++, eventually adopted in C++11." - https://research.swtch.com/plmm https://research.swtch.com/plmm
jl6 4y ago
Perhaps computer architecture is destined to become like building architecture: functionally complete, with variation only in form, aside from some minor incremental innovations and the occasional one-off megaproject.
- rowanG077 4y ago
  I'm not an architect, but I very, very, much doubt building architecture is complete. Just look at buildings from 30 years ago to now. The differences are stark.
  - jl6 4y ago
    It’s all form. Buildings 30 years ago and buildings today do almost exactly the same things. Sure there have been marginal improvements, but they are marginal.
    - rowanG077 4y ago
      No it's not all form. Ventilation, climate control and light have changed a lot in recent years. At least from my amateur point of view.
      - fallingfrog 4y ago
        I don't know, my house was built in 1920 and it's doing fine. Upgrades have been made- heat pumps, new wiring and so forth- but the overall design of the house isn't really that different from one built today. Except that in my house, the 2x4's are actually 2 inches by 4 inches.
        rowanG077 4y ago
        That doesn't mean your house would be build like it's 1920 if it were build right now. Besides I didn't really mean "normal" houses. But rather large buildings which have complex ventilation, sunlight, climate control and sustainability requirements. There has been a lot of innovation in that space. And it shows in the office buildings that are build today.
v4dok 4y ago
Maybe the sophons are doing their work. Seems like a fundamentals problem to me.
PicassoCTs 4y ago
I wonder, as parallelism is exhausted too, will there be a point of reversion, were the cost of bad management practices on product and performance become so big, that the decision power returns to the experts who craft such systems? As in, the council of engineers vote no on middle managements eternal bloat for company internal status points? Else the users switch to engineer governed systems, as created by open source?
mclightning 4y ago
Some headlines could really use capital letters. I am not a native speaker, and I struggled to understand this sentence until I clicked on the link, and realised it is actually a headline-style sentence...
bovermyer 4y ago
Something I would like to see pursued is a race to the bottom - of power consumption, that is. Is it physically possible to produce a chip that consumes no power? How would that be done? What would be required? Is anyone asking questions like that?
- krapp 4y ago
  No... no one is asking questions like that because a chip that consumes no power but still does work would be greater than 100% efficient and would violate the laws of thermodynamics.
  - bovermyer 4y ago
    Well sure, but exploring the _idea_ of zero power consumption might lead to interesting discoveries in efficiency and power consumption models, even if actually achieving 0% power consumption is impossible.
    - deleted 4y ago
      [deleted]
- sc0ttyd 4y ago
  No, because that would violate the laws of thermodynamics.
- contingencies 4y ago
  Yes, if the problem is viewed broadly, eg. passive packages like RFID tags. Power consumption has been a focus area in chips since forever. For active chips, it's not possible if the problem is viewed narrowly however it's possible to have a package that contains both power generation capability (eg. solar, kinetic) and highly power efficient, sporadic processing which probably exist already. Major application areas would be long-lived deployments (eg. animal tags, probes, implants, wearables).
tyho 4y ago
Apple, Google, Microsoft and Amazon should buy out ARM and collectively run it as a non profit.
whoisthemachine 4y ago
I have a hard time viewing something that can "run out of steam" as a "fundamental law". It seems to me that the true fundamental laws - those of physics - are going full steam ahead, and the reality they describe are catching up to companies' chip designers (and marketers).
akkartik 4y ago
"More-than-Moore has created a compelling case for the implementation-analyses microcosm to transcend across the fabrics of system design, from silicon to package, and even beyond, and more so in the systems companies that are at the bleeding edge of design innovation." What does this even mean?
- Rexxar 4y ago
  It means that marketing division has won against engineering division.
- tbjoern 4y ago
  This reads like GPT-3. Perfect example of syntax without semantics.
UltraViolence 4y ago
I predicted a LONG time ago that once we reached the physical limits computers would get bigger. Starting out with chiplet designs and then moving on to dinner-plate type systems such as Cerebras. Our computers will become larger in size, maybe the size of a fridge in a couple of decades. Power requirements too will increase. I'm still hoping some wondrous material will be invented which will allow us to shrink chips still further. But it's obvious there's a limit how far we can go. The theoretical limit is still way off, though. It's about several million times the speed of current CPU's.
- N1H1L 4y ago
  We will definitely move to wide bandgap semiconductors fast, where we can run much higher switch speeds (aka clock rates) without overheating
  - UltraViolence 4y ago
    I once read an article in Popular Science in the early 80's about the invention of quantum transistors at Texas Instruments. Are those what you mention?
    - N1H1L 4y ago
      Not really. Our substrate today is silicon (really n-type silicon). We build a city on top of that substrate. Modern semiconductors have become way more heterogenous in recent years. Our gate insulators are not silicon dioxides anymore but high-k dielectrics such as hafnium oxide. And even interconnects now have different compositions, such as cobalt and copper. But the substrate is still holding us back, and one reason for that is creating high-quality single crystal wafers for silicon that are way more manageable. The solution for a long time has been to use direct bandgap semiconductors such as GaN, AlN, and so on. Silicon is an indirect bandgap semiconductor, meaning its conduction and valence bands are not aligned in momentum space. As a result, electrons hopping between these bands pay a thermal penalty. GaN and AlN don't have that problem, and we now have a plethora of crystals (especially complex oxides) that are all direct, and we have an entire library of bandgaps to choose from. The problem is that we cannot easily make wafers from these direct bandgap systems. At least yet to be on any commercial scale. Honestly, rather than flushing billions of dollars down the toilet for Zuck's vanity projects - we should have spent money to scale up Czochralski's growth[1] for a ton of crystal families. But, as we are reaching the limits for reticule sizes and we move to chiplet architectures, maybe smaller wafers will work too? [1] https://en.wikipedia.org/wiki/Czochralski_method https://en.wikipedia.org/wiki/Czochralski_method
EmilioMartinez 4y ago
Whatever happend to photonic computing? I can't find anything about how distante is the state of the art from being economically feasible

229 points by _hypx 4y ago

This graph in the article is pretty fascinating: https://i0.wp.com/semiengineering.com/wp-content/uploads/Picture1-2.png https://i0.wp.com/semiengineering.com/wp-content/uploads/Pic... (not really a png, apparently, but a webp file)

Traubenfuchs 4y ago
More depressing -number of cores will also level off eventually and where does that leave us then? Will we actually have to optimize our code instead of pushing each hello world request through hundreds of function calls? I also assume some niches are actually already 90%+ optimized. Once the cores level off it‘s stagnation here too.
- deleted 4y ago
  [deleted]
- joe_the_user 4y ago
  Would the number of cores in a GPU level off? It seems like intensive computing of all sort will migrate to gpgpu programming.
  - Traubenfuchs 4y ago
    Shrinking has almost stopped too and you can only make a chip that big before it runs into other constraints.
    - singularity2001 4y ago
      There is a lot of room for development before the exponential curve can be carried by the next paradigm: at least for desktop computers we are still decades away from case filling 3D "compute cubes".
      - brazzy 4y ago
        It's quite possible that kind of thing has hard limits set by cooling.
        singularity2001 4y ago
        sure but usually before hard limits are reached a new paradigm is ready to take over
    - plasticchris 4y ago
      The wafer scale computing folks would disagree...
      - Traubenfuchs 4y ago
        This is insane. https://www.eetimes.com/powering-and-cooling-a-wafer-scale-die/ https://www.eetimes.com/powering-and-cooling-a-wafer-scale-d...
  - ummonk 4y ago
    Seems like the latest Nvidia GPUs aren't really an improvement over the previous ones, but just bigger and proportionally more expensive. So maybe the leveling off in performance is already starting to happen.
    - brokenmachine 4y ago
      That is not true. The 4090 uses less power than a 3080ti while being 63% faster. https://www.techpowerup.com/review/nvidia-geforce-rtx-4090-founders-edition/39.html https://www.techpowerup.com/review/nvidia-geforce-rtx-4090-f... , and 45% better performance than a 3090ti while using 2% less power (at 4k). https://www.techpowerup.com/review/nvidia-geforce-rtx-4090-founders-edition/32.html https://www.techpowerup.com/review/nvidia-geforce-rtx-4090-f... Can't find the link now, but I saw a youtube video where they did an analysis of it at different wattage limits and it performed very nicely. 4090 draws a lot of power, but Nvidia has just chosen to work at the diminishing returns end of the curve. It's a halo product for people who will pay for the top of the range. I mean, look at the price!
- mschuster91 4y ago
  I'd guess we get more hardware acceleration. In classic computers (PCs, laptops, servers), for stuff like audio/video codecs, that's been available for decades, but I'd say the next big push will be ethernet/wifi accelerators that do stuff like checksum calculation/verification, VLAN tagging or even protocol-level stuff like TLS in the chip itself - currently, that's all gated for expensive cards [1], I'd expect that stuff to become mainstream over the next few years. Another big part will be acceleration for disk-to-card data transfer [2] - at the moment, data is being shifted from the disk to RAM to GPU/other compute card. Allowing disks to interface with compute cards will be a lot of work - basically, there needs to be a parallel filesystem reader implementation on the disk itself, on the DMA controller or in the GPU, which is a lot of effort to get done right with most modern and complex filesystems - but in anything requiring high performance removing the CPU bottleneck should be well worth the effort. Mobile is going to be more interesting because of power, space and thermal constraints and a lot of optimization already being done because unlike on classic computers vendors couldn't just go and use brute force to get better performance, and there is a bit of an upper cap on chip/package size as well. Probably we'll see even more consolidation towards larger SoCs that also do all the radio communication stuff if not on the same chip then at least in the same package, so the end game there is one single package that does everything and all that's needed on the board are RF amplifiers and power management. All the radio stuff will move to SDR sooner or later, allowing for far faster adoption of higher bandwidth links and with it, a reduce in power consumption as the power-expensive RF parts have to be powered on for less time to deliver the same amount of data. [1] https://docs.nvidia.com/networking/display/FREEBSDv370/Kernel+Transport+Layer+Security+%28kTLS%29+Offloads https://docs.nvidia.com/networking/display/FREEBSDv370/Kerne... [2] https://developer.nvidia.com/blog/gpudirect-storage/ https://developer.nvidia.com/blog/gpudirect-storage/
  - rjsw 4y ago
    Network offload has been available in low-cost controllers for a long time, TLS isn't common though. It could be better if network controllers just had a documented local CPU, then the firmware could be extended over time to add new features.
- JohnJamesRambo 4y ago
  What if aliens show up and they are thousands of years ahead of us and they don’t have anything much more powerful than an i9 running their UFO?
  - ars 4y ago
    Then that pretty much spells the end of true AI. We may shift to computers that operate off of chemical signals instead of electrical ones - like the brain.
  - bee_rider 4y ago
    Who knows what sort of tech aliens would have? I don't think this whole foray into general purpose computing was necessarily pre-destined. Maybe their whole system could look more like a bunch of strung-together ASICs. "You made your computers drastically less efficient so that anyone could program them? Why would you want your soldier-forms and worker-forms to program computers? Just have the engineer-forms place the transistors correctly in the first place, duh."
    - rl3 4y ago
      >Who knows what sort of tech aliens would have? I don't think this whole foray into general purpose computing was necessarily pre-destined. It's sometimes fun to think that technology is a function of the intelligence that creates it. What if the aliens have some vastly different perception of reality than us? Things we consider obvious to them may not be, and vice versa. The underlying desires and motivation different. Humans for example, often tend to invent things for the sake of it. Imagine a species that doesn't do that. Or an organic FTL drive conjured into existence over eons via distributed intelligence. Weird.
      - checkyoursudo 4y ago
        > Or an organic FTL drive conjured into existence over eons via distributed intelligence. Weird. E.g., What if the first aliens to find us are hyperintelligent slime molds, whose entire existence is predicated on finding the shortest distance between two points in higher-dimensional space and then traveling there to see what there is to eat?
- pbazarnik 4y ago
  The "cores" are becoming more specialized and optimized for domain specific tasks. Compiler technology advancements are needed to take advantage of such heterogenous architectures in a transparent way. LLVM MLIR started that already.[1,2] The alternative is being stuck with each silicon vendor's proprietary solutions like CUDA. [1] https://mlir.llvm.org/ https://mlir.llvm.org/ [2] https://www.theregister.com/2022/04/04/compiling_the_future/ https://www.theregister.com/2022/04/04/compiling_the_future/
- tyingq 4y ago
  There's also ideas like the Mill processor. Though it's hard to avoid comparisons to Itanium, and how a mountain of money still didn't produce a compiler that could unlock what initially sounded like a better ecosystem.
- Frost1x 4y ago
  >More depressing -number of cores will also level off eventually and where does that leave us then? Short of breakthroughs (e.g. quantum and currently unknowns), the only clear path is less generalized architectures and more specialized chips. As you move more towards ASICs from general architectures you get improved performance, reduced power, and so on. We've lived in the era of software where hardware was abundant and cheaper than an engineers time. Throw more hardware at it and make sure you have generally optimal algorithms in most your run paths. That's going to change more and more and I suspect we're going to have to start rethinking or redeveloping some layers of abstraction between current software and hardware. As it stands now we're building more and more complex things atop weaker intermediary layers of abstraction to save time and meet budgets but that's going to have to be revisited in the future and the inefficiency debts we've been building up will need to be paid down. Clear code will become less of a top priority when clever optimizations can be added in that may not be so clear. We're still many many year away from this but that's my prediction.
  - urthor 4y ago
    Not necessarily a problematic trend. It takes thousands and thousands of engineers to produce a general purpose chip. It takes... one smart lady to optimize a widely used library for FPGA acceleration.
- duped 4y ago
  The metric is performance per watt per dollar. At the moment the fact is that the amount of compute available per watt dollar is ridiculously cheap, crypto not withstanding. We are not limited by compute resources but by business practices. The organizational cost of software design is where the next gains are, not technological.
- stn_za 4y ago
  Can't wait. People should be so ashamed that what's basically an IRC client (Slack) requires more than 4GB of ram and so many cores. Laziness. Truly.
MereInterest 4y ago
Back in grad school, one of the analysis programs I used dated back to the mid 70s. The original paper gave a performance metric for a test program, which I compared to the runtime on a Chromebook running Linux. I was curious how closely that scaled with Moore's Law, and computed "initial_release + (1.5 years)*log2(initial_runtime/current_runtime)". That is, assuming that the change in program speed has increased due to hardware improvements, and those hardware improvements follow Dennard scaling, what year is it? This (admittedly very rough) measurement ended up giving 2003. It was wrong by over a decade from the actual date, but correctly gave the date at which clock frequencies stopped improving.
nullifidian 4y ago
Not sure if it's exactly accurate with the plateauing trend -- single-threaded performance almost doubled in the last 5 years.
- pclmulqdq 4y ago
  It's a log scale graph, it shows a doubling. The performance just isn't increasing as fast as it was before.
  - hansel_der 4y ago
    yea, buying a pc in the early intel era was a somewhat double edgded sword because you knew that the next generation would come out in a year or so and it would probably have more than double the performance.
    - Nomentatus 4y ago
      For many years my friends and I had a rule that we wouldn't buy a new computer until it offered at least 4X the speed of our old one. We didn't have to wait all that long.
mrandish 4y ago
My entire career in computers spans the 40 years in that graph. The constant leaps in fundamental speed were exhilarating and kind of addictive for technologists like myself. As the rate of progress has fallen off over the past decade it's been sad to see the end of an era. I'm sure speeds and capabilities will continue to increase, albeit much more gradually, but significant gains are going to come slower, harder and at greater cost. The burden will have to be shouldered by system architects and programmers in finding clever ways to squeeze out net gains under increasingly severe fundamental constraints (density, leakage, thermals, etc). Back when I started programming as a teen in 1980 with 4k of RAM and ~1 Mhz 8-bit CPUs, knowledge of the hardware underneath the code and low-level assembly language skills were highly valuable. Over the years, the ability to think in instruction cycles and register addressing modes grew anachronistically quaint. Now I suspect those kinds of specialized 'down-to-the-metal' optimization skills may see a resurgence in value.
- zaptrem 4y ago
  This graph shows transistors basically maintaining pace and completely disregards multi-core performance. Of course single core perf will rise more slowly when a chip now has 8-64x as many cores.
  - StillBored 4y ago
    Which is great if you have a traditional server application servicing a lot of independent requests, or giant linear equations that can be solved in parallel. OTOH, the graph has an amadal's law section, which for many tasks is pretty out of steam (aka desktop web browsing/javascript JIT/etc). I'm not going to be so stupid as to say 8 cores should be enough for anyone (while attached to a machine with 128) but you have to wonder if the stable diffusion style apps running on your desktop are going to be mainstream, or isolated to the few who choose to _need_ them as a hobby or a smaller part of the public that uses them for commercial success. AKA, I can utilize just about every core i'm given with parallel compiles, or rendering a 4K video, but I'm pretty sure i'm the only one in my immediate family that needs that. My wife in the past might have done some simulation work, but these days the heaviest thing she runs on her PC is office products. This really gets back at the Arm big.little thing, where you really want 99% of your application usage to run on the big cores. The little cores only exist for background/latency insensitive tasks, and the odd case where the problem actually can utilize a large number of parallel cores and needs to maximize efficiency in the power envelope to maximize computation. AKA throw a lot of lower power transistors at the people rendering video/etc, and leave them powered off most of the time. AKA, put another way, the common use case is a few big powerful cores for normal use, playing games, whatever with one or two high efficiency processors for everything else and a pile of dark silicon for the rare application that actually can utilize dozens of cores because its trivial to parallelize and doesn't work better being offloaded to a GPU. I suspect long term intel was probably right with larrabee, they were just a decade or two early. So, economically I don't see people buying machines with a couple hundred cores that sit dark most of the time. Which will drive the price up even more, and make them less popular.
causi 4y ago
This trend of browsers to increasingly lie to me about what I'm looking at is infuriating.
- modeless 4y ago
  The URL is a lie but that's not the browser's fault. It's correctly showing you the URL that you requested and the server responded to. If you save the file locally the browser will give it the correct extension.
- q-big 4y ago
  > This trend of browsers to increasingly lie to me about what I'm looking at is infuriating. The browser does not lie to you, it just does not show the MIME type of the content. I do agree that it would make sense that the browser shows the MIME type of the content that is currently displayed, but this is opposition to the current fashion (in particular pioneered by Apple) of "simplifying" everything.
  - deathanatos 4y ago
    > The browser does not lie to you, it just does not show the MIME type of the content. In this particular case, Firefox does: > Picture1-2.png (WEBP Image, 1054 × 593 pixels) is the title on the tab. (The ".png" comes from the URL, as a sibling notes.) Chrome does not.
deleted 4y ago
[deleted]
samstave 4y ago
where the heck is Transmeta ??? intel was so afraid of them in 1997 Obv AMD was the true and once... but there was a lot of Transmeta-fear back then too
- jecel 4y ago
  Transmeta announced their first product, the Crusoe processor, in 2000. Before then they were highly secretive and nobody knew what area they would compete in. Intel was indeed worried about the laptop market when the Crusoe came out, but quickly adopted the voltage and frequency scaling into their own processors negating some of Transmeta's key technical advantages. Meanwhile, IBM changed directions as a third party fab (they dropped bulk CMOS to focus on SiliconOnInsulator) leaving Transmeta without a product to sell until they could find a new fab and design their next generation product for that.
amelius 4y ago
How is it that the number of transistors still grows exponentially, while the power use has plateaued?
- deleted 4y ago
  [deleted]
- eru 4y ago
  Each transistor uses less power?
  - amelius 4y ago
    Exponentially less.
- Swenrekcah 4y ago
  I think I can say the following. Smaller transistors mean fewer electrons that go in and out every clock cycle, so less power per transistor. Higher clock frequency means more cycles per second, that is more electrons spent per second thus higher power consumption. Since clock frequency has stabilised and the total area of a chip is I think not much larger than before, it is expected to see the power consumption stabilising. I also believe I read somewhere that one of the reasons clock frequency stoped increasing was that the power consumption became too high for the chips to handle the thermal dissipation.
joshspankit 4y ago
I wonder how much of that flattening is because chips are now hovering just under the 5GHz/6Ghz wifi frequencies. Yes we have techniques that help them avoid each other, but it seems like it would be enough of a tech and PR hassle that companies wouldn’t bother.
- hansel_der 4y ago
  pretty sure it has something to do with speed of light divided by clock speed
  - kloch 4y ago
    Pretty sure it has everything to do with heat dissipation
    - hansel_der 4y ago
      probably true as well. also iirc the actual clock of the logic gates is a factor above the 'operations clock'
  - joshspankit 4y ago
    I hadn’t even considered that there is a physical limitation. I’m too lazy to look it up now, but when I first read this I feel like the math said electrons can move at maximum 5cm in a single 5GHz clock cycle? That’s wild.
    - hansel_der 4y ago
      the eletrons do not have to 'move' the entire way for transfer of information because they will push the already present ones further.
      - joshspankit 4y ago
        Well yes, but that’s an academic difference unless you’re stating that they can transfer information faster than light.
jdthedisciple 4y ago
interesting, so basically since 2010 no all-to-significant progress has really been made despite the scaling in logical processor count. This is considering the vast majority of software basically still uses only a single core
- dspillett 4y ago
  > the vast majority of software basically still uses only a single core And that which does use multiple cores, sometimes only scales well to a few because then other bottlenecks† start to become most significant. Many things are not so “embarrassingly parallelisable” that they can easily take full advantage of the power available from expanding the number of processing units available beyond a certain point. -- [†] things no longer being “friendly” to the amount or arrangement of shared L2/L3 cache as the amount of threads grow causing more cache-thrashing, hitting other memory bandwidth issues, or for really large data you might be considering issues as far down as the IO subsystem or network.
andy_ppp 4y ago
I’d love to see how GPUs fit into this picture; are we getting more transistors on a die but designs are not getting much faster?
abbeyj 4y ago
You might like https://github.com/karlrupp/microprocessor-trend-data https://github.com/karlrupp/microprocessor-trend-data

shadowgovt 4y ago

I wonder how long until software will also need to shift. The hardware can only become so parallel before the software will have to change to more closely match its reality.

hinkley 4y ago
I think there’s a potential for collaboration between borrow checkers and more aggressively NUMA architectures, but the problem is you still have to run commercial operating systems on any chips you make. That’s less of a problem for embedded systems and controllers, but then you lose a lot of the value as well.
IshKebab 4y ago
That was one of the few good parts of this article. Software will have to become power-aware. You already see that on phones where software has to schedule tasks with the OS rather than running them whenever it wants.

cudgy 4y ago

For consumer use and probably many commercial uses too, I am becoming skeptical about hardware performance improvements and whether users are gaining sufficient benefits from these improvements. Software has become so wasteful of resources that the hardware improvements are offset and there is little perceptible improvement for the end user. This is of course not the fault of the chip makers, but the fault of the movement to inefficient web apps and more resource intensive languages and frameworks.

jiggawatts 4y ago
I find myself agreeing with Jim Keller. His stance — from very high up in the chip design industry — is that individual teams at the bottom may be seeing the end of the road, but there are alternate paths being explored by other teams. Often these alternate paths aren’t yet commercialised — mere options — but enable the overall improvements to keep going without getting stuck. Some examples: Stacking and joining chiplets will soon enable over 2 TB/s memory bandwidths for ordinary devices, far higher than the 50 GB/s typical of mid-tier DIMM memory. Storage latency and IOPS is still going up. Millions of random accesses per second with ~20 microsecond latencies enabled technologies like DirectX DirectStorage. This totally changes the way game engines work and how their art assets are authored. I could go on…

snvzz 4y ago

RISC-V has been engineered to support this very shift. It can thus be the base ISA for all these accelerators to be built on.

Taniwha 4y ago
I'm a RISC-V designer, I'm afraid it's not a magic bullet for these sorts of issues. What it does do is free lots of designers to work on solutions and build off of each other's work

vinyl7 4y ago

I look forward to Moore's law ending, because then software might actually become good again (lol probably not)

FPGAhacker 4y ago
No kidding, almost 30 years later and windows still finds a way to make my work computer run like crap. Looking at a flame graph 60 levels deep demonstrates the problem pretty well I think.
iveqy 4y ago
Software seems like a very immature field where we can still do a lot to increase performance. I'm looking forward to the shift
- vinyl7 4y ago
  Software has become more immature over the last decades because developers lost the engineering mindset and skills to write optimized software like they could back in the days where we only had a couple of MB of ram. It really does not require new expertise or tech at all to cut latency and load times by 90%. Programmers have to get back to being engineers instead of just duct taping libraries together or praying that the dumb GC knows what its doing
  - hajile 4y ago
    Are customers willing to pay 10x the cost for the mildly better experience? At most places, there’s barely enough time to implement things completely let alone to optimize everything properly. It’s also noteworthy that optimizing 10kloc from yesteryear is a much easier task than optimizing a few mloc of code today. We didn’t just lose all those optimized libraries. The requirements bloated and nobody wants to reduce features.
    - vinyl7 4y ago
      I would argue that the only reason we went from 10kloc to +1mloc is because of the proliferation of bad coding practices...like OOP

sp332 4y ago

Moore's law is not a fundamental law, it's just an observation. Amdahl's law is holding just as well as ever.

amirhirsch 4y ago
Amdahl’s law is also just a conjecture unless you have a proof that P is disjoint from NC

kayson 4y ago

The article doesn't really mention one of the biggest problems: cost. These new process nodes are insanely expensive. Far moreso than before. This is one of the biggest drivers of new packaging technologies (chiplets). Companies simply can't afford to manufacture their entire design on the latest process. There are even still newer transistor designs that promise further improved performance but will be even more cost prohibitive. I'm not convinced that there are any hard EDA problems here, despite the fact that EDA as an industry in general is woefully archaic, especially when compared to the equivalent in the software world. We've been doing multi-layer and/or multi-die packages for a long time. It's more of a project management challenge, having to get different teams (process, packaging, design, verification) to work together earlier on in the design cycle, and more frequently throughout.

conjecTech 4y ago
Chiplets aren't so much driven by a need for heterogenous processes as much as minimizing the yield impact of defects. Ian Cutress has a good portion covering it in this recent video: https://www.youtube.com/watch?v=oMcsW-myRCU https://www.youtube.com/watch?v=oMcsW-myRCU. In short, if your process produces 20 defects per wafer, and you can fit 100 chip on a wafer, you're going to end up with ~84% yield(ie, slightly less than 20% loss). If you are able to split that same chip into 2 equal-sized pieces and make twice as many, your yield is now above 90%. AMD has also made them composable in such a way that they have to produce and stock far fewer ICs to fulfill all of their SKUs, which is also another fantastic benefit.
- kayson 4y ago
  Absolutely. Yield is obviously a big part of cost-per-die, but it's not just defect density related. When a node is first released, the process is not as well controlled so you end up with yield loss because the process doesn't match the models (in the extremes) and dies fail at various testing stages. This obviously gets better over time, but it's still a major issue for companies designing in the latest technologies. Anecdotally I'd say there's a ~3X reduction in the "sigma" of the process over 3-5yrs. Of course these issues have always existed, but wafer costs have never been so high, and yields never so low (both because of increased defect density and worse process control with new transistors).

travisgriggs 4y ago

If we start shifting towards specialized hardware configurations to solve specialized problems, how does “move everything to the cloud communicating through fragmented docker images” fit? It just seems weird to me to see posts of spending lots of money on complicated scalable Kubernetes clusters, but at the same time people are putting their AI computation engines right on die so that they get good cache coherence. Maybe they’re more resolvable than it seems.

c54 4y ago
K8s GPU nodes are already kind of an example of this-- the app can still access the specialty capabilities of the hardware, we just have to make sure to tell the scheduler "hey run this app on this kind of node with this flavor of capabilities". I could imagine that kind of flavor capability growing and becoming more fleshed out Except k8s calls it 'taints' which is uh a weird choice.
- kevincox 4y ago
  Taints is a funny name when you look at it like that but taints are actually the opposite half of the story. If you want a Pod to be scheduled with a certain node you need to add affinity. The taints are to ensure that your average nginx pod doesn't run on the specialty hardware and block the pods that actually need it. In theory the scheduler could be smart enough to evict the pods that don't need the special node but IDK if the kube scheduler is smart enough. Even then it may he preferable to have the taint though to reduce the eviction rate.
bippingchip 4y ago
This is probably one of the biggest challenges ahead, likely more so than making hardware that still somehow scales despite Moore’s law slowing down and tapering out entirely. The increased scale of integration with advanced 3D packaging and chiplets is a nice way forward, but the heterogeneity of those solutions need innovation at the programming model as much as anything else: how do you make such a complex system accessible in a way that the programmer can actually use it efficiently? As much as I like semiengineering and their articles, they are very hardware and process technology focused and tend to miss the software side of things.

lumost 4y ago

I wonder if part of the recent switch back to statically typed languages is merely a reflection of changing compute requirements. During my career, single core performance has only doubled at best. Scale out has worked… but it hasn’t been cheap.

grumpyprole 4y ago
Or perhaps because knowing/reasoning about at least some properties before running a program is a good thing? Optimisation is only one consequence of static types. Perhaps the reason is that static type systems are getting better and less intrusive.

prng2021 4y ago

I love buying new and better gadgets like everyone else but if cpu advancements froze after the next generation of ones using the 3nm transistor node, would life on Earth really be that bad? We’d be in a world where we have no choice but to optimize existing algorithms, software, and hardware designs. And yes, after many years even that would reach its limits. Even so, I still think life would be great for every generation that lives on after that.

FrontierPsych 4y ago
It really makes no difference to most people. I have 10 and 15 year old computers and they work just fine for me. Web browsing, spreadsheets, word processing documents. I don't use the latest gamer stuff, or have 285-dimensional graphics that rotate in 48 dimensions or whatever. I'd think that 95% of the computer users are just like me. Pissed me off...my parents essentially use their computer and smart phones the same exact way - email,browse the web, and that's about it. My siblings decided they had to upgrade and got them new computers and smartphones. WTF? Total waste of maybe $5000. If anyone else has $5000 that they want to spend on nothing, let me know and I will give you my bank routing number and account number and you can just send it to me for nothing in return, too. :P
1123581321 4y ago
I would personally be content, but I’m thankful for the advances made possible by faster computing, especially in medicine, and I’d like to see more. If we keep advancing computing power, today’s research supercomputers will be tomorrow’s personal computers in the hands of researchers of all income levels all over the world.
- jiggawatts 4y ago
  The vast majority of hardware devices haven’t even caught up to 14nm, let alone 3nm which is still an experimental node used by a few customers “at risk”. It would take decades at the current pace of progress just for everyone to catch up to the current bleeding edge. I would have retired from IT work by the time that happens! In other words, we’re already at the stage that many people will continue to see non-stop improvements even if 3nm is “the end”. Meanwhile Intel says that their 18A node is looking good and ahead of schedule…

lob_it 4y ago

Dating back to the turn of the century, I can still recall the pleasure of building my 1st of many SMP desktops/workstations with an Abit VP6 to game on and work on at home. In 2022, I would almost expect to see mobo designers and chip manufacturers start rolling out deca-socket designs for compute and automotive use, giving users (okay.. Just the nerds and geeks) the option of mixing-and-matching chips to accomodate custom configurations (and unthought of use cases). The CPU wall almost reminds me of automotive where the engines may be hitting cooling/fuel system limits of the current technologies, but still has plenty of optimizations available for unsprung weight, torsional rigidity, coefficient of drag and so on. It may not address the power efficiency angles, but for many users, having 10 sockets to add optimized compute chips (main cpus, AI accelerators, graphics enhancement chips and a number of other feature-enhanced chips) keeps the R&D money flowing until the industry gets over this next hurdle (they always do). The author states that the expense of pushing moores law, etc is becoming cost prohibitive, so take a break and rock some modern PCB designs.

davidgay 4y ago
> In 2022, I would almost expect to see mobo designers and chip manufacturers start rolling out deca-socket designs for compute and automotive use It's called the PCIe bus. And before you say "but it doesn't meet my needs / it's latency is too high / it's bandwidth is too low", come up with some ideas on how to do that better rather than just say "add sockets".
- lob_it 4y ago
  I rocked a Commodore 128.. Don't F with me :p Power is nothing without spittle (I'm sure at least one person said it) I'm not familiar with the lingo, but I was thinking of multilayer sockets, with a higher bandwidth loop/ring for the primary sockets with the PCIe coming off the CPUs in a traditional fashion. Perhaps I read about that with the opterons ages ago.
  - davidgay 4y ago
    86=lda a (which I still remember), is all I have to say.

stopdropnhotpot 4y ago

They're still predicting shift away from silicon is another 5 years out. No, really. It's been 20 years+ at this point they've been developing alternatives and they can make chips but they're far from being competitive with silicon in any metric. It's called single crystal complex oxide or SiC

DeathArrow 4y ago

Can't we move over from silicon? I've read about countless tries to design CPUs based on different principles and materials like carbon, optical and even biological modeled systems. So far our best results still come from trying to shrink silicon transistors.

prox 4y ago
With so much invested in Silicon it is hard to boot up a whole new paradigm. In that sense working with Silicon is much easier / less friction relatively speaking.
- jiggawatts 4y ago
  I hear that the plan is (roughly) to try and grow thin layers of something like silicon carbide (SiC) on top of silicon wafers.
easygenes 4y ago
The current long-term roadmaps put a rough target of 2036 for this to be practical. [1] 1: https://youtu.be/TwgvJSOa09M?t=495

DeathArrow 4y ago

If power, heat and efficiency are valid concerns, we might as well try to optimize the software, use less abstractions, go for the code that use the least CPU cycles, use less interpreted languages, more AOT compiled ones.

TaylorAlexander 4y ago
In general, sure, for things like web pages etc. In fields like robotics people are always desperately trying to improve the efficiency of their algorithms but it really seems like we just need way more powerful silicon.

bullen 4y ago

What they are doing now is trying to separate power and data, so that they approach the die from different sides. But the memory bottleneck cannot be solved so we are stuck with the CPU performance per watt we have had since Ivy Bridge around 2012. DRR3 has lower latency than DDR4,5,6+ GPU is also stuck. The ONLY solution is to code vanilla Java (no/few external deps.) on the server and mostly C with ++ compiler on the client. Forget Rust, Go, WASM, etc.

bheadmaster 4y ago
> The ONLY solution is to code vanilla Java (no/few external deps.) on the server and mostly C with ++ compiler on the client. > Forget Rust, Go, WASM, etc. Why?
- bullen 4y ago
  Because you need a VM with GC on the server so it doesn't crash and can share memory between cores properly. On the client you can go lower since deploying new buggy code only affects some of the clients and not the entire server (unless you deploy completely untested patches). - Rust seg. faults. - Go has no VM - WASM has no GC.
  - bheadmaster 4y ago
    How exactly are GC and VM crucial to "not crashing" and "sharing memory"? And what exactly do you mean by "not crashing"? Crashing is a broad term, and I assume you mean C++-style-crash-because-of-type-safety-errors. Go does not run on VM, yet is type safe. Rust can indeed cause segfaults, but that's only if you (ab)use the "unsafe" mechanism, which is explicitly labeled as not safe. As long as you stick to the safe Rust, segfaults are impossible. Could you explain your reasoning to me in a little more detail, please?
    - bullen 4y ago
      "While I'm on the topic of concurrency I should mention my far too brief chat with Doug Lea. He commented that multi-threaded Java these days far outperforms C, due to the memory management and a garbage collector. If I recall correctly he said "only 12 times faster than C means you haven't started optimizing"." - Martin Fowler https://martinfowler.com/bliki/OOPSLA2005.html https://martinfowler.com/bliki/OOPSLA2005.html "Many lock-free structures offer atomic-free read paths, notably concurrent containers in garbage collected languages, such as ConcurrentHashMap in Java. Languages without garbage collection have fewer straightforward options, mostly because safe memory reclamation is a hard problem..." - Travis Downs https://travisdowns.github.io/blog/2020/07/06/concurrency-costs.html https://travisdowns.github.io/blog/2020/07/06/concurrency-co... "Inspired by the apparent success of Java's new memory model, many of the same people set out to define a similar memory model for C++, eventually adopted in C++11." - https://research.swtch.com/plmm https://research.swtch.com/plmm

jl6 4y ago

Perhaps computer architecture is destined to become like building architecture: functionally complete, with variation only in form, aside from some minor incremental innovations and the occasional one-off megaproject.

rowanG077 4y ago
I'm not an architect, but I very, very, much doubt building architecture is complete. Just look at buildings from 30 years ago to now. The differences are stark.
- jl6 4y ago
  It’s all form. Buildings 30 years ago and buildings today do almost exactly the same things. Sure there have been marginal improvements, but they are marginal.
  - rowanG077 4y ago
    No it's not all form. Ventilation, climate control and light have changed a lot in recent years. At least from my amateur point of view.
    - fallingfrog 4y ago
      I don't know, my house was built in 1920 and it's doing fine. Upgrades have been made- heat pumps, new wiring and so forth- but the overall design of the house isn't really that different from one built today. Except that in my house, the 2x4's are actually 2 inches by 4 inches.
      - rowanG077 4y ago
        That doesn't mean your house would be build like it's 1920 if it were build right now. Besides I didn't really mean "normal" houses. But rather large buildings which have complex ventilation, sunlight, climate control and sustainability requirements. There has been a lot of innovation in that space. And it shows in the office buildings that are build today.

v4dok 4y ago

Maybe the sophons are doing their work. Seems like a fundamentals problem to me.

PicassoCTs 4y ago

I wonder, as parallelism is exhausted too, will there be a point of reversion, were the cost of bad management practices on product and performance become so big, that the decision power returns to the experts who craft such systems? As in, the council of engineers vote no on middle managements eternal bloat for company internal status points? Else the users switch to engineer governed systems, as created by open source?

mclightning 4y ago

Some headlines could really use capital letters. I am not a native speaker, and I struggled to understand this sentence until I clicked on the link, and realised it is actually a headline-style sentence...

bovermyer 4y ago

Something I would like to see pursued is a race to the bottom - of power consumption, that is. Is it physically possible to produce a chip that consumes no power? How would that be done? What would be required? Is anyone asking questions like that?

krapp 4y ago
No... no one is asking questions like that because a chip that consumes no power but still does work would be greater than 100% efficient and would violate the laws of thermodynamics.
- bovermyer 4y ago
  Well sure, but exploring the _idea_ of zero power consumption might lead to interesting discoveries in efficiency and power consumption models, even if actually achieving 0% power consumption is impossible.
  - deleted 4y ago
    [deleted]
sc0ttyd 4y ago
No, because that would violate the laws of thermodynamics.
contingencies 4y ago
Yes, if the problem is viewed broadly, eg. passive packages like RFID tags. Power consumption has been a focus area in chips since forever. For active chips, it's not possible if the problem is viewed narrowly however it's possible to have a package that contains both power generation capability (eg. solar, kinetic) and highly power efficient, sporadic processing which probably exist already. Major application areas would be long-lived deployments (eg. animal tags, probes, implants, wearables).

tyho 4y ago

Apple, Google, Microsoft and Amazon should buy out ARM and collectively run it as a non profit.

whoisthemachine 4y ago

I have a hard time viewing something that can "run out of steam" as a "fundamental law". It seems to me that the true fundamental laws - those of physics - are going full steam ahead, and the reality they describe are catching up to companies' chip designers (and marketers).

akkartik 4y ago

"More-than-Moore has created a compelling case for the implementation-analyses microcosm to transcend across the fabrics of system design, from silicon to package, and even beyond, and more so in the systems companies that are at the bleeding edge of design innovation." What does this even mean?

Rexxar 4y ago
It means that marketing division has won against engineering division.
tbjoern 4y ago
This reads like GPT-3. Perfect example of syntax without semantics.

UltraViolence 4y ago

I predicted a LONG time ago that once we reached the physical limits computers would get bigger. Starting out with chiplet designs and then moving on to dinner-plate type systems such as Cerebras. Our computers will become larger in size, maybe the size of a fridge in a couple of decades. Power requirements too will increase. I'm still hoping some wondrous material will be invented which will allow us to shrink chips still further. But it's obvious there's a limit how far we can go. The theoretical limit is still way off, though. It's about several million times the speed of current CPU's.

N1H1L 4y ago
We will definitely move to wide bandgap semiconductors fast, where we can run much higher switch speeds (aka clock rates) without overheating
- UltraViolence 4y ago
  I once read an article in Popular Science in the early 80's about the invention of quantum transistors at Texas Instruments. Are those what you mention?
  - N1H1L 4y ago
    Not really. Our substrate today is silicon (really n-type silicon). We build a city on top of that substrate. Modern semiconductors have become way more heterogenous in recent years. Our gate insulators are not silicon dioxides anymore but high-k dielectrics such as hafnium oxide. And even interconnects now have different compositions, such as cobalt and copper. But the substrate is still holding us back, and one reason for that is creating high-quality single crystal wafers for silicon that are way more manageable. The solution for a long time has been to use direct bandgap semiconductors such as GaN, AlN, and so on. Silicon is an indirect bandgap semiconductor, meaning its conduction and valence bands are not aligned in momentum space. As a result, electrons hopping between these bands pay a thermal penalty. GaN and AlN don't have that problem, and we now have a plethora of crystals (especially complex oxides) that are all direct, and we have an entire library of bandgaps to choose from. The problem is that we cannot easily make wafers from these direct bandgap systems. At least yet to be on any commercial scale. Honestly, rather than flushing billions of dollars down the toilet for Zuck's vanity projects - we should have spent money to scale up Czochralski's growth[1] for a ton of crystal families. But, as we are reaching the limits for reticule sizes and we move to chiplet architectures, maybe smaller wafers will work too? [1] https://en.wikipedia.org/wiki/Czochralski_method https://en.wikipedia.org/wiki/Czochralski_method

EmilioMartinez 4y ago

Whatever happend to photonic computing? I can't find anything about how distante is the state of the art from being economically feasible