_chris_

17 ms·

121.
by _chris_ 9y ago
The current version (v1.10) should be forward-compatible, and I believe is expected to be fully ratified in the next two months. There has been very little churn on it for a while now. [Edit: RISC-V Linux is being upstreamed, and rocket-chi
122.
by _chris_ 9y ago
> using an entirely different CPU core, the Berkeley Rocket Chip Nope, the U54 and E31 are both Rocket, just with different parameters/configurations. SiFive has continued to improve Rocket and contribute their improvements back t
123.
by _chris_ 9y ago
> Most people downsize once their kids leave home Except you can't do that in California, because then you're walking away from your Prop 13 "rent-controlled" property taxes.
124.
by _chris_ 9y ago
I find the idea that master is the default is exactly why it should not be the development branch. For open-source software, that's what people download and try to build -- it should always strive to be production ready.
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by _chris_ 9y ago
The gcc port is mature and has been upstreamed. The LLVM port is still a work-in-progress. I know there's been at least one talk presenting some thesis work on an clock-less RISC-V design at an early RISC-V workshop, but I'm not a
126.
by _chris_ 9y ago
Interesting question! I think the FOSSi community (behind LibreCores and ORConf) are probably the most aware of what that road map is and helping us get there. One of the issues is that cores are fun to build, but are only one piece of the
127.
by _chris_ 9y ago
Yah, you can ask questions, I might just have to give evasive answers ;). This tech report itself isn't embargoed or I wouldn't have posted it. The pre-publication issue is the scope of what I could cover in this tech report was r
128.
by _chris_ 9y ago
BOOM is a core that fits into the rocketchip SoC ecosystem. Or said another way, BOOM wears rocketchip's skin. :D [i.e., caches, memory system, uncore, test harnesses...] Default rocketchip uses the Rocket core, which is a single-issue
129.
by _chris_ 9y ago
I was using Coremark in that report, which is what ARM used to market their cores. The 32b ARMv7 cores have NEON SIMD, but I believe no FMAs, whereas BOOM is 64b and includes double-precision FMA units. Also there's no current RISC-V e
130.
by _chris_ 9y ago
No. The beauty of RISC-V is it has a compressed extension with 2-byte forms of the most common instructions. The average instruction size is 3.0 bytes on SPECint workloads. That's even better than x86. So instead of creating a 4-byte
131.
by _chris_ 9y ago
The ISA is going to have close to zero impact on a processor's performance. I actually wrote up another tech report on this topic ( https://arxiv.org/abs/1607.02318 ). In short, you can rely on macro-op fusion to dy
132.
by _chris_ 9y ago
Hi dnautics! Dynamic scheduling isn't as complicated as it seems, especially now that we have so many transistors on a chip and Amdahl performance is still very critical for most applications. However, the value of OoO isn't just
133.
by _chris_ 9y ago
> Chris, I worked hard to get you on that pedestal, don't go jumping off. ;- ) O:-) > ARM[v7] maybe does a little bit more per instruction, what with those conditions and 14+ character non-mnemonic mnemonics; but ultimately in
134.
by _chris_ 9y ago
Hi phkahler! This is just a short workshop report with a focus on the microarchitecture (edit: oh! and the report mentions a 24% reduction in clock period). Unfortunately, some conferences have very strict pre-publication rules that prevent
135.
by _chris_ 9y ago
Sadly no. You would still have to broadcast the 3 write ports to each copy, so "being closer" doesn't actually work out.
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by _chris_ 9y ago
Hi, author here. Just to point out to others (and to be fair to the A15), IPC is just one part of the final performance equation. =)
137.
by _chris_ 9y ago
Yes, a few ISAs have things like "branch.likely", but the CPU will just ignore it because it will do a better job anyways (the compiler is only as good as the test program used to guide its analysis). GCC allows the programmer to
138.
by _chris_ 9y ago
"We postulate that the original study produced good results because it evaluated the new scheduler in a machine whose performance bottleneck lay outside the execution core. The problems introduced by the steering logic were, as a resu
139.
by _chris_ 9y ago
why doesn't my body dump all the fat, since I'm eating a surplus of calories anyway? That's a great research question. Normally, the body tries to maintain a happy "set point" of fat. However, different genetic po
140.
by _chris_ 9y ago
As far as I can tell, MIT didn't have a CS department until 1975 (when it was added to the EE department to become EECS; the same year Irene Greif in the OP got her PhD). Before the 70s, many schools considered CS as part of a Math deg
141.
by _chris_ 9y ago
> meal kits Food at MIT is a very interesting topic. The administration has been pushing "dining halls" and "mandatory meal plans" for 15 years now, thinking that college should be a Disneyland resort experience you c
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by _chris_ 9y ago
The real Pilot 2021 website: https://studentlife.mit.edu/housing/undergraduate-housing/re... The administration of MIT have decided to nuke a dorm whose culture they didn't like and forced everyone to leave (
143.
by _chris_ 9y ago
x for "fixed point". r for "register" is too vague.
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by _chris_ 10y ago
Can you compile linux with llvm?
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by _chris_ 10y ago
And also that Sinbad did dress up as Sinbad the Sailor as host of an afternoon of Sinbad movies in 1994.
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by _chris_ 10y ago
- The bus is something called TileLink which is their own protocol so all your peripherals have to be compatible or wrappers have to be made. FYI: TileLink is not a RISC-V thing, it's a Berkeley/SiFive rocket-chip processor thin
147.
by _chris_ 10y ago
I'd like to know what the problem was with ARM's ISA that presented problems for superscalar. Load/store multiple, for starters. Even just load-pair-increment-address is a pain as it requires 3 write ports. https:/&#x
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by _chris_ 10y ago
Incredibly easy at the assembler level, harder if you want the compiler to understand/schedule it for you.
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by _chris_ 10y ago
the ARM core only runs at 40MHz I wouldn't be surprised if that's purely a licensing/price discrimination issue, and not a technical issue. Either way, an other argument for RISC-V.
150.
by _chris_ 10y ago
In that class students design and implement in logic gate level simulator a 32-bit RISC CPU. 6.004 is a ton of fun. If you want to build something, I recommend a CISC-like multi-cycle design that uses micro-code (or a hardware sequencer)

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