Interesting question! I think the FOSSi community (behind LibreCores and ORConf) are probably the most aware of what that road map is and helping us get there.

Interesting question! I think the FOSSi community (behind LibreCores and ORConf) are probably the most aware of what that road map is and helping us get there. One of the issues is that cores are fun to build, but are only one piece of the puzzle (guilty!). So there are lots of FPGA-targeting softcores, but fewer cache coherent high-performance multi-level cache systems, for example. I'm hoping that SiFive's TileLink protocol helps shore up the ecosystem, which is a high performance free and open bus standard. Some other gaps are devices, drivers, graphics, crypto-engines, more open-source testing/verification infrastructure... it's an exciting time for OSHW!