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> Chris, I worked hard to get you on that pedestal, don't go jumping off. ;- ) O:-) > ARM[v7] maybe does a little bit more per instruction, what with those co
by _chris_ 9y ago
> Chris, I worked hard to get you on that pedestal, don't go jumping off. ;- )
O:-)
> ARM[v7] maybe does a little bit more per instruction, what with those conditions and 14+ character non-mnemonic mnemonics; but ultimately instruction counts should be pretty close, right?
Great question. I just so happen to have written a tech report on this very topic! https://arxiv.org/abs/1607.02318 https://arxiv.org/abs/1607.02318
Basically, performance should be identical between ARMv8 and RISC-V, given the RISC-V core implements macro-op fusion to combine things like pair loads together.
- microcolonel 9y ago> Great question. I just so happen to have written a tech report on this very topic! https://arxiv.org/abs/1607.02318 https://arxiv.org/abs/1607.02318 . > Basically, performance should be identical between ARMv8 and RISC-V, given the RISC-V core implements macro-op fusion to combine things like pair loads together. Yeah, I drew my conclusions from your papers. :- ) I really should diversify my sources, I bring nothing to this exchange.