4 ms·
- The bus is something called TileLink which is their own protocol so all your peripherals have to be compatible or wrappers have to be made. FYI: TileLink is
by _chris_ 10y ago
- The bus is something called TileLink which is their own protocol so all your peripherals have to be compatible or wrappers have to be made.
FYI: TileLink is not a RISC-V thing, it's a Berkeley/SiFive rocket-chip processor thing. And it has an AXI interface on it anyways.
- gluggymug 10y agoSorry I am just basing this off what I can find. I don't see AXI mentioned in the SiFive docs when I skim through.