In that class students design and implement in logic gate level simulator a 32-bit RISC CPU. 6.004 is a ton of fun. If you want to build something, I recommend

In that class students design and implement in logic gate level simulator a 32-bit RISC CPU. 6.004 is a ton of fun. If you want to build something, I recommend a CISC-like multi-cycle design that uses micro-code (or a hardware sequencer) to dramatically reduce the HW costs (pdf warning): http://inst.eecs.berkeley.edu/~cs152/sp13/handouts/microcode.pdf http://inst.eecs.berkeley.edu/~cs152/sp13/handouts/microcode... And it could still run a RISC ISA like Beta or RISC-V.