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The ISA is going to have close to zero impact on a processor's performance. I actually wrote up another tech report on this topic (https://arxiv.org/abs/1607.02
by _chris_ 9y ago
The ISA is going to have close to zero impact on a processor's performance. I actually wrote up another tech report on this topic (https://arxiv.org/abs/1607.02318 https://arxiv.org/abs/1607.02318).
In short, you can rely on macro-op fusion to dynamically fuse some idioms that show up as instructions in other ISAs, like load-pair.
- monocasa 9y agoWouldn't relying on macro op fusion increase i$ pressure?
- _chris_ 9y agoNo. The beauty of RISC-V is it has a compressed extension with 2-byte forms of the most common instructions. The average instruction size is 3.0 bytes on SPECint workloads. That's even better than x86. So instead of creating a 4-byte "load-pair" instruction (or having to fuse two 4-byte loads), you can fuse two 2-byte loads into a single "load-pair" micro-op. Same performance, same code density, but a cleaner ISA (since not everybody wants the complexity of implementing load-pair).