3 ms·

Hi, author here. Just to point out to others (and to be fair to the A15), IPC is just one part of the final performance equation. =)

microcolonel 9y ago
Chris, I worked hard to get you on that pedestal, don't go jumping off. ;- ) Fair enough, you didn't reach the same frequencies, but that's what the other 1.4mm² and the process shrink are for. ARM[v7] maybe does a little bit more per instruction, what with those conditions and 14+ character non-mnemonic mnemonics; but ultimately instruction counts should be pretty close, right? Update: also probably SIMD[or vectors], breakpoints, more interesting memory management, the handling of bizarre FP corner cases, maybe power management[high frequency dvfs? :- )], and other things go in that additional 1.4mm².
- _chris_ 9y ago
  > Chris, I worked hard to get you on that pedestal, don't go jumping off. ;- ) O:-) > ARM[v7] maybe does a little bit more per instruction, what with those conditions and 14+ character non-mnemonic mnemonics; but ultimately instruction counts should be pretty close, right? Great question. I just so happen to have written a tech report on this very topic! https://arxiv.org/abs/1607.02318 https://arxiv.org/abs/1607.02318 Basically, performance should be identical between ARMv8 and RISC-V, given the RISC-V core implements macro-op fusion to combine things like pair loads together.
  - microcolonel 9y ago
    > Great question. I just so happen to have written a tech report on this very topic! https://arxiv.org/abs/1607.02318 https://arxiv.org/abs/1607.02318 . > Basically, performance should be identical between ARMv8 and RISC-V, given the RISC-V core implements macro-op fusion to combine things like pair loads together. Yeah, I drew my conclusions from your papers. :- ) I really should diversify my sources, I bring nothing to this exchange.

3 ms·

Hi, author here. Just to point out to others (and to be fair to the A15), IPC is just one part of the final performance equation. =)

by _chris_ 9y ago

microcolonel 9y ago
Chris, I worked hard to get you on that pedestal, don't go jumping off. ;- ) Fair enough, you didn't reach the same frequencies, but that's what the other 1.4mm² and the process shrink are for. ARM[v7] maybe does a little bit more per instruction, what with those conditions and 14+ character non-mnemonic mnemonics; but ultimately instruction counts should be pretty close, right? Update: also probably SIMD[or vectors], breakpoints, more interesting memory management, the handling of bizarre FP corner cases, maybe power management[high frequency dvfs? :- )], and other things go in that additional 1.4mm².
- _chris_ 9y ago
  > Chris, I worked hard to get you on that pedestal, don't go jumping off. ;- ) O:-) > ARM[v7] maybe does a little bit more per instruction, what with those conditions and 14+ character non-mnemonic mnemonics; but ultimately instruction counts should be pretty close, right? Great question. I just so happen to have written a tech report on this very topic! https://arxiv.org/abs/1607.02318 https://arxiv.org/abs/1607.02318 Basically, performance should be identical between ARMv8 and RISC-V, given the RISC-V core implements macro-op fusion to combine things like pair loads together.
  - microcolonel 9y ago
    > Great question. I just so happen to have written a tech report on this very topic! https://arxiv.org/abs/1607.02318 https://arxiv.org/abs/1607.02318 . > Basically, performance should be identical between ARMv8 and RISC-V, given the RISC-V core implements macro-op fusion to combine things like pair loads together. Yeah, I drew my conclusions from your papers. :- ) I really should diversify my sources, I bring nothing to this exchange.