_chris_

19 ms·

151.
by _chris_ 10y ago
Thanks for the plug, but just to clarify, while BOOM approaches the cycles/instruction of Intel's server cores, it does not approach their clock frequencies! Still, I'd say its competitive with the current mobile processor se
152.
by _chris_ 10y ago
Performance solely depends on the design team and their market targets, not the ISA ( https://arxiv.org/abs/1607.02318 ).
153.
by _chris_ 10y ago
Yup, the problem is that Berkeley's dev work is funded by public money, which means they can't vacate their "ownership", because it's the public's.
154.
by _chris_ 10y ago
> That doesn't rule out that there is some optimal compressed ISA that is a lot better than what RISC-V provides. There's an entire PhD thesis on the RISC-V compressed ISA (RVC) and it shows that RVC's compression comes fa
155.
by _chris_ 10y ago
Yikes, my spell checker missed that. -.- (shakes fist at OSX).
156.
by _chris_ 10y ago
> Is there even any point of referring to an ISA as distinctly 'RISC' or 'CISC' anymore? First, you need to be careful to not confuse the ISA with the micro-architecture. RISC and CISC are descriptions of the interfac
157.
by _chris_ 10y ago
> I'm curious how you would relate your work to WISC (Writable Instruction Store Computers) and how you view WISC machines? You know, I've never heard of WISC machines before. I think the idea of RISC though is you are basicall
158.
by _chris_ 10y ago
> But instead of suggesting that we ignore instruction count, the paper seems to suggest that we need to consider both instruction and µop count. Why? In part because I have nothing else to go on! Not every processor gives me a uop cou
159.
by _chris_ 10y ago
I would love to chat with the ARM guys and pick their brains. I suspect for a few things (like unfused branches) they wanted to match the existing micro-ops they were already generating since they would still have to support ARMv7! But I&#x
160.
by _chris_ 10y ago
> The fallacy is believing that somehow you are a better pathfinder than they are and you would not make their choices in their position. RISC-V has two huge advantages going for it; 1) they got to learn from 40 years of mistakes, and 2)
161.
by _chris_ 10y ago
I compiled the x86 code using gcc 5.3 using mtune/march=native and -O3. It just turns out that the gcc compiler generates entirely scalar code for SPECInt!
162.
by _chris_ 10y ago
The title is cutting out an important part of my report's story: "Avoiding ISA Bloat with Macro-Op Fusion ". You can still specialize your processor to eke out more performance, but you (often) don't need to change th
163.
by _chris_ 10y ago
Oh man, that was fast. I didn't tell anybody I had released this yet, and here it is! Uhhh, AMA?
164.
by _chris_ 10y ago
lowrisc.org? This stuff takes time. Also there are shipping products using RISC-V, but they aren't user accessible (e.g., cameras).
165.
by _chris_ 10y ago
I'm gonna go out on a limb and guess "memory model"; both consistency and coherence issues.
166.
by _chris_ 10y ago
Huh? RISC-V with the compressed extension is incredibly efficient in its encoding. Better than x86 or ARM in both static and dynamic bytes per program. Also, Icache pressure is a huge problem in modern warehouse-scale computers. Any proce
167.
by _chris_ 10y ago
x86 is NOT dense - it averages nearly 4 bytes per instruction on workloads such as SPEC. And not everybody wants to go through the design effort to support variable-length encoding (it's non-trivial and can potentially increase pipelin
168.
by _chris_ 10y ago
8086 was put together in just a few weeks, once it was clear Intel needed a "stop-gap" ISA, as their other design (432) was taking too many years to put together. And it shows. The operations they blew 1-byte instructions on is a
169.
by _chris_ 10y ago
I'm not sure this should be called "RISC". It seems very tightly coupled to the particular processor pipeline being proposed: It has dynamic typing (each register has a tag telling you what type of data it currently holds). S
170.
by _chris_ 10y ago
Looks like they're getting rid of a ton of seat-space so they can add a third set of doors? Huh?
171.
by _chris_ 11y ago
> Efficient integer overflow should really be implemented in the processor. I disagree. It greatly adds to the complexity, verification, cost, and power for the HW to do this, which is especially onerous in that almost nobody cares or r
172.
by _chris_ 11y ago
I'm confused by SPECInt throwing overflows - did the blogger verify the output matched the golden spec? I assume he did, but I'd really like verification. With SPEC it's really easy to use a wrong compiler flag or make a chan
173.
by _chris_ 11y ago
Yes. You can do whatever you want, even extending or changing the ISA as you want (though if you break I-subset compatibility, the only thing you can't do is still call it a RISC-V processor).
174.
by _chris_ 11y ago
There are a million things that influence performance to a greater degree than the ISA. However, there's no reason to believe you can't make a perfectly good high-performance RISC-V processor. In my own benchmarking of ARM, x86,
175.
by _chris_ 11y ago
> This is a paper CPU, right? What? No, it's an Instruction Set Architecture. It's the language the CPU speaks. > Multiply and divide as an option belongs down at the 50 cent 8-bit CPU that runs a microwave oven, not on som
176.
by _chris_ 11y ago
I believe Jan Gray was only implementing RV32I, but he was manually laying out the core and the router himself! You can find his slides here ( http://riscv.org/workshop-jan2016.html ).
177.
by _chris_ 11y ago
The problem with SPEC is it is a 1990's workstation benchmark suite... should my cell phone processor's design be guided by how quickly it can compile ia32 code? Or simulate quantum computers?
178.
by _chris_ 11y ago
Chisel? There are dozens of non-Chisel RISC-V cores out there already (and many more that are closed source and being used by companies like Bluespec and Rumble).
179.
by _chris_ 11y ago
The studies I've seen have shown that the FU mix is heavily skewed and changing on every basic block, particularly when you offload the DLP to a more efficient vector/SIMD unit. I'm not sure I see how MT would solve the mix p
180.
by _chris_ 11y ago
There's a chapter in the current RISC-V manual that explains how you could make a RISC-V-like VLIW ISA. But VLIW is most certainly NOT the "future". VLIW demands an even "mix" of instruction types, and that's

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