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TSMC to begin 3nm chip production next month

393 points by carlycue 4y ago

Kye 4y ago
It's hard to remember looking at such tiny marginal improvements that they do compound over successive generations. "Only" a few percent is the difference between the Apollo computers and being able to simulate them with Redstone in Minecraft on a consumer computer over the gap of time that separates them.
- sho_hn 4y ago
  Can we herald Minecraft-Redstone as the new universal virtual machine that does what WASM couldn't?
  - Kye 4y ago
    Give it time. Someone will make the JRE run on WASM and wipe away the distinction.
    - jeroenhd 4y ago
      > Someone will make the JRE run on WASM https://teavm.org/ https://teavm.org/ Minecraft contains some native dependencies, though; you'll need something like https://copy.sh/v86/ https://copy.sh/v86/ or https://bellard.org/jslinux/ https://bellard.org/jslinux/ with the right operating system image to run it in browser.
  - muttled 4y ago
    Can't wait for my machine to come to a crawl as I walk up to some machine the size of a city and find out it's actually mining crypto
klxmarket 4y ago
Does anyone have rumors/insider knowledge about the progression of Epyc/Threadripper? Threadripper seems insanely expensive right now, will the next generation be faster at least or use less energy? Or, in other words, does it make sense to wait?
- gjsman-1000 4y ago
  Threadripper appears to be basically dead for most markets, being slowly cannibalized by the standard Ryzen platform.
  - bryanlarsen 4y ago
    Cannibalized from the bottom by Ryzen and from the top by Epyc (aka Threadripper Pro).
- zitterbewegung 4y ago
  Threadripper pro is going to be the only workstation that makes sense anymore. Consumer threadrippers are being phased out. This is all public knowledge . You are better off with high end Ryzen now .
- freemint 4y ago
  Almost all Threadripper capable silicon ends up in Epyc. Once AMDs server market share is saturated Threadripper will come back. The reason why Intel is looking to push new HEDT is because their server market share is decreasing.
- ptomato 4y ago
  Threadripper is pretty reasonably priced; a 5995WX is about $101/core, or about 3% more than a Epyc 7773x for 10% more performance. For comparison, a Xeon Platinum 8380, which has roughly similar perf per core, costs $224/core. Sure, consumer CPUs are a bit cheaper; i9-12900kf is about $45/core (though half of those are slow cores) and 5950X is about $34/core, but price discrimination for server lines has always been fairly standard. I think the least expensive you can get into Epyc Milan is around $55/core, but that's on a part that only needs half the cores on an 8-core chiplet to be functional; the 7773x needs all of them, for 8 chiplets, and the 5995WX is that but with even tighter binning for higher clocks.
- trynumber9 4y ago
  Genoa, from which the next generation TR will likely derive, is up to 96 cores in 12 N5 chiplets with a new N6 IO chiplet that supports PCIe5 and 12 channel DDR5. It has some added instructions (AVX512) and will likely be more efficient at the same clock rate but they will be pushing the clocks higher instead. I would not wait around unless you have plenty of time. I doubt a cut down Genoa will show up on workstations until the server market is satiated.
hardware2win 4y ago
Why do we waste state of art, bleeding edge CPUs manufacture capabilities on some telephones? Who needs phones this fast?
- colinmhayes 4y ago
  Because 95% of people think their computers are fast enough but want more battery life on their phone I suppose.
  - TheMode 4y ago
    Until you discover that any new performance/efficiency discovery gets spent on more bloated software.
  - hardware2win 4y ago
    My random ass phone survives something like a few days of random usage Do we need more?
    - JshWright 4y ago
      Have you considered that your usage pattern may be atypical?
      - hardware2win 4y ago
        Yes, but I dont believe that theres this many phone addicted ppl
        sho_hn 4y ago
        You don't have to be phone-addicted for your phone usage to keep going up. In a lot of societies ever more daily tasks continue to migrate off PC and onto phone apps. The number of services you interact with primarily through your phone (say, booking a hairdresser appointment or getting notified your dry-cleaning is done) keep going up everywhere. People use their phone for contactless NFC payments, for public transit check-in/check-out, etc. Having enough charge to last the day becomes increasingly not optional. Everyone gets habituated by context to look at the thing more and more as the gateway to everything.
bogomipz 4y ago
I had a question. I apologize if this a bit naive. The first slide shows the N3 releases go though 2025 and then we see the arrival of N2. How significant are these numbers in regards to end of Moore's law? Will we saw N1 in the next 10 years or is that getting to a process that requires something radically new like carbon nanotubes etc?
- arroz 4y ago
  Idk if Moore’s law is still in effect as stated It isn’t actually a law, it is more of an observation / prediction But people have been inventing new technologies to be able to still improve chips (for instance, finfets and now GAA)
- mastax 4y ago
  Completely insignificant. They're just names. Intel is going "Intel 4" -> "Intel 3" -> "Intel 20A". Everyone will call them 4nm, 3nm, 20Å (Angstrom) despite them explicitly not being that, but it's a hard industry habit to break.
- mastax 4y ago
  I'll also mention that we should have reasonable node progress through 2030 at least. There's plenty of room at the bottom with just EUV multi-patterning and a few other very practical improvements. Beyond that I'm less hopeful but I wouldn't bet against it.
- TooKool4This 4y ago
  I think this is not the correct way of thinking of Moore's law. Like mentioned elsewhere, Moore's law is not so much a law as a self-fulfilling prediction. Semiconductor companies follow Moore's law (or recently an approximation) to stay competitive because their competitors do it and hence Moore's law continues. The cost of not marching along to Moore's law can mean you will get left in the dust (see Intel). I think a better question to ask is whether the underlying economic factors behind continuous process tech improvements are healthy. Is there enough value-add to the final user by continuous process tech improvements? Are the costs for that improved process tech scaling with the value-add? And is the competitive landscape healthy? While that holds true, companies will keep looking for process tech improvements to give them a competitive edge. In the 80-90s this was very much true but in recent decades it was to a lesser extent hence why we see consolidation/reduction in the number of foundries, foundry services to amortize the cost of older node-tech, and R&D going to companies/partnerships that can capture the most end user value-add (Apple/TSMC). Looking forward I think the economics are very healthy with a design-house/foundry service model that we have right now so I would guess that Moore's law (or some approximation) will continue for the next decade. There are a lot of process tech innovation that can lead to better performance that are not necessarily scaling related. In fact, scaling transistors stopped being very useful a while back afaik due to the breakdown of Dennard's scaling.
pvsukale3 4y ago
Can someone who is into chips explain how big of a thing this is? And what maybe next?
- ksec 4y ago
  >And what maybe next? N2 in 2025. N1.4 or may be N14A in 2027. Roughly N1 in 2030. I believe we will hit an economic wall by the end of this decade. i.e The cost of Next Gen node exceed what the market are willing to pay for it.
- adam_arthur 4y ago
  The biggest gains in performance and efficiency almost always come from moving to newer gen manufacturing. So pretty big deal for computing. We may be close to the age where most laptops are fanless, for example. Most non apple devices still on 7-11nm equivalents since apple gets first dibs on new gen fabs from TSMC (pay for the right)
  - drexlspivey 4y ago
    > We may be close to the age where most laptops are fanless, for example. Correct me if I’m wrong but high performance fanless laptops are only possible with ARM chips atm. Has any other big laptop chip designer even announced plans for anything remotely close to M1/M2?
    - adam_arthur 4y ago
      Most efficiency gains come from manufacturing fab process, not whether it's ARM or x86. M1 is the only 5nm processor on the market right now. Yes, you will see quite comparable performance once Intel and AMD get to 5nm as well
      - jasonwatkinspdx 4y ago
        Architecture does still matter. M1's decoder is 8 issue. You just can't build that for x86 without pipeline depth or some other resulting tradeoff making it pointless.
nicolaslem 4y ago
From the outside, having Apple securing the latest and greatest nodes for so long feels kind of anti-competitive. Apple has been selling phones and laptops with N5 for two years and I don't think we still have any competing product in the hands of consumers using N5 yet. If I'm not mistaken Nvidia and AMD are about to release products using N5.
- klelatti 4y ago
  We probably have 3nm production on this timescale because of the long term relationship between Apple and TSMC and the $100bn + that Apple have spent with TSMC over that time period. No one else has done this. Apple pays the money and takes the risks, so they get the rewards.
  - ohgodplsno 4y ago
    "Takes the risks" Takes what risks ? Buying the riskless new transistors that TSMC puts out because they know that they work ? Apple taking risks would be making the chips themselves (see: the failure that was itanium and how it screwed Intel because they had to reorganize their facilities for it), not buying it wholesale and just having TSMC print it.
    - klelatti 4y ago
      The risk that TSMC doesn't deliver on node improvements / deliver the relevant SoCs in the required numbers. And if you think that risk is small / nil I would point you to Intel's recent track record. And just to point out that Apple actually does bear the risk you've highlighted as Itanium was a design (which Apple does) not a manufacturing failure.
      - lotsofpulp 4y ago
        There is also risk that sufficient consumers do not want to buy Apple’s products at a sufficient price premium to offset the price premium that Apple paid to TSMC.
alberth 4y ago
Seems like this missed Apple's M2 / iPhone 14 release by a few months.
- bee_rider 4y ago
  I think the it must be more outside the window than the release dates make it seem -- Apple must, I guess, do some QA and build up a decent stockpile before the release of a new iPhone.
- bongobingo1 4y ago
  Luckily it will be around for the M3 and iPhone 15... and the M4 and 16... and ... The lead time would be enough, that I doubt M2 was ever going to be a 3nm chip.
  - jamiek88 4y ago
    I read that it was. The M2 was backported to the N5 process due to pandemic delays. I can’t actually find anything other than ‘analyst states’ type links though.
- Slartie 4y ago
  It's not like they have 3nm chips ready the day after production. When they "begin production", it takes months until the first actual, working chip from that production leaves the fab. And then it's not like the day after, Apple could produce iPhones or Macs with those chips. It takes months from having the first chip in hand until production churns out volumes of finished devices.
  - wtallis 4y ago
    This article is specifically about the high-volume manufacturing milestone, which can be over a year after the first working chips leave the fab.
- whynotminot 4y ago
  Unfortunate. That will be three straight iPhones on essentially the same node, which I think hasn't happened yet. Might also lead to some awkwardness for Apple in having to port a design running on an older node to a newer one, if M3 does use 3nm. By all accounts, and if the pattern holds true, the M[n] chip is generally the scaled up version of the latest A series design. So if we have a release of A15 on 5nm, and the M3 is going to be based off that design, but ported to 3nm, that's kind of an interesting situation.
syntaxing 4y ago
Pardon my ignorance on this subject, but at 3 nm, don’t you get into some weird quantum artifacts because the layers are so stupidly close? Curious how that is addressed?
- coolspot 4y ago
  Not “layers”, but “features”. 3nm is basically a pixel size for chip schematics, it doesn’t mean that they draw 1px features with it.
  - samstave 4y ago
    This was always my understanding is that the litho(?) mechanism can "print" in 3nm resolution, which allows the overal scaling of all features to be based on this "pixel" resolution. I was dumbfounded when even hearing about 14NM YEARS before it was a thing (I also got to see 64-core concepts at intel in ~1999 or so) 3nm is mind boggling amazing. Whatever happened to "voxels" (before the graphics term, intel was creating "voxels" that were used to use light to transfer vertically between layers... but I stopped following CPU arch years ago.
    - agar 4y ago
      hah, I remember when "submicron technology" was the bleeding edge of chip design. :-) https://cordis.europa.eu/project/id/554 https://cordis.europa.eu/project/id/554
  - ajross 4y ago
    It's not even that. Nothing in a modern process node is as small as the node size, and in fact with modern processes it's not even close. I just checked, and per some reference on wikipedia TSMC 3nm's metal pitch is expected to be 24nm (so, ~12nm wide metal "wires" on the lowest level of interconnect are the smallest things you'll see on a picture). What's been happening is that fabs have been exploiting more and more tricks to increase transistor density while still using the larger feature sizes. So flat transistors became finfet's, increasing their gate area and allowing chips to use fewer of them for the same silicon area, etc... So read "3nm" as "a process with the same transistor density as you would expect had some ancestral ~90nm process been shrunk by a factor of 30".
Kukumber 4y ago
They are 1 innovation away to become in a position with no way to compete The knowledge and education backlog is way too high for the West Scary times
- api 4y ago
  Hey but we maximized shareholder value.
- upupandup 4y ago
  meh Samsung already started 3nm chip production last month and they are not facing an imminent invasion https://www.theverge.com/2022/6/30/23189362/samsung-3nm-chips https://www.theverge.com/2022/6/30/23189362/samsung-3nm-chip...
  - Kukumber 4y ago
    "invasion"? what do you mean exactly? you meant reunification? i don't see how that could be a problem, we do business with China already, it would just become one of their state, you can still trade with them Or you meant as a result the US would not be able to steal the fabs, tech and workforce? (and by steal i mean purchase, just like we write about how China is stealing our tech when they purchase patents or by other deep internal means) Samsung is in a worse position than intel, not only it is Korean, and they have problems with their northern neighbor, as well as with Japan, but they also got hit by the anti-competitive behavior and trade war from the US, and were told to stop development of their in-house chip (Exynos), to place Qualcomm as a western leader, despite their poor tech https://old.reddit.com/r/Android/comments/71rjyx/why_exynos_is_not_used_by_samsung_in_the_us/ https://old.reddit.com/r/Android/comments/71rjyx/why_exynos_... And i'm not sure if The Verge is a trustable source, they either have insider knowledge or their source is manipulative, because that contradicts with the Exynos story If what they claim is true, then that'll be interesting to see if their "promise" can become a reality, time will tell But as a matter of fact, still nothing is happening in the west, and that was my entire point
    - wing-_-nuts 4y ago
eis 4y ago
So I wonder if the M2 Pro/Max/Ultra will after all be on the N3 node. If N3 HVM starts next month, the A15 being on N5P and it being a year until the A16 on N3 will be released and Apple being the first to use N3... some other Apple silicon needs to use the capacity first, or am I missing something?
- BoardsOfCanada 4y ago
  All I've heard is that they (M2 pro+) will all be on the N3 node, which would indicate release in the first months of next year.
- msbarnett 4y ago
  All of the M1/Pro/Max/Ultra shared the same fundamental core design. Presumably the same will be true of the M2 series. As someone else here said, fab nodes are more like Lego blocks than a printer’s dpi – moving a design to a new node means rebuilding it in terms of the new node’s building blocks, not just “shrinking the design”. So if the M2 Pro/Max/Ultra are intended to follow the same “reuse the cores (possibly rearranged) with more GPU blocks/cache etc” it seems unlikely. But if the make a design break within the M2 series then it’s possible? I’d expect Apple to follow their historical behavior and lead with the next A-series phone processor on the new node first. M1 Pro/Max/Ultra chips have huge surface areas – since process defect rates are driven down over time, it makes sense to start with your smallest chips first, so that you can get good yield out of your big chips once the defect rate is lower.
  - adam_arthur 4y ago
    Intel famously followed the "tick-tock" model where they would alternate between designing a new architecture and then moving that architecture to a new processing node. So not sure it's true that you can't shrink down a largely similar architecture from one process to another. Obviously it's fallen off the wagon a bit here, but seems more due to operational issues at Intel than it being fundamentally not doable https://en.wikipedia.org/wiki/Tick%E2%80%93tock_model https://en.wikipedia.org/wiki/Tick%E2%80%93tock_model
unixhero 4y ago
Are these the same 3nm as Intel operates with? Or are we seeing nano-meter inflation again, in such a way we did with Gigahertz...?
- trynumber9 4y ago
  Gigahertz are still the number of cycles. That didn't inflate, it correlates to a real timing. TSMC call it N3 instead of 3nm for a reason. It's not 3nm.
  - zerocrates 4y ago
    Gigahertz weren't inflated per se, but there were similar effects to the name games with process nodes with clockspeeds when those were more directly seen as indicators of performance. I'm thinking particularly of AMD having Athlon model numbers that were 1:1 to clockspeeds for years, then Athlon XP switching to ones that were above their actual speeds, to sort of vaguely indicate which Intel clockspeed they were claiming performance parity with. Of course once they were beyond the clockspeed-above-all Pentium 4, Intel themselves stopped focusing on marketing clockspeeds and things gave way to basically arbitrary naming/numbering schemes. (Or to some extent, core counts.)
    - 0x457 4y ago
      Well, performance is roughly = clock speed * instructions per cycle. When intel was dominant (pre-Anthlon XP and pre-Core era), Clock speed alone could have been used to measure performance. Then, AMD Athlon XP come out with higher IPC than Pentiums, but the customers were used "Higher clock, higher performance" even though Athlon XP was faster at the same clock speed. So, they've changed model names to indicate performance parity, that was the game intel played. They didn't lie or mislead about clock speeds anywhere.
      - zerocrates 4y ago
        That's my point: this seems to me more less exactly where we are now with "Intel 7" being their "10 nm but better-er" process and the previously-known-as-7nm becoming "Intel 4." They're saying, well, the actual nanometer number has long been a little wishy-washy anyway, so we're jettisoning the pretense that this is a measurement of anything in particular and just picking a number that sounds better and aligns with our competition's numbers. And of course it's not just Intel marketing this way, everyone does, but their more recent naming change makes it more transparent. Tired of years of saying "welll, TSMC's Xnm (or X number with no units that's sort of implied to be nm) is really equivalent to our X+Ynm," they just go for marketing on parity. Like I said in the start of my previous post, this isn't actually inflating (or deflating as the case may be) but it's just taking a concept that's widespread among the consumers as a proxy for quality/value and marketing to that idea rather than any actual physical characteristic.
deleted 4y ago
[deleted]
sylware 4y ago
china invasion too?
marcodiego 4y ago
If any chip manufacturer can hear me: please, change this metric to transistor per square millimeter. Thanks!
- szatkus 4y ago
  That wouldn't work. Transistors density depends on what you're going to build. And there are other variations between processes.
- wtmt 4y ago
  Do you mean transistors per cubic millimeter? Cubic centimeter (cc) may be a better choice since it’s already a more common measure of volume at smaller scales for most of the world.
  - wtallis 4y ago
    Areal density rather than volumetric density will continue to be the most relevant basis for comparison as long as chips are still being fabricated on wafers with a fixed total area. Flash memory has been 3D for years but the important density measurement correlated to cost is still Gbit/mm^2.
  - IshKebab 4y ago
    No, cubic mm makes no sense because transistors are created on the surface of the wafer. It's surface area that matters. You can't get more transistors by using a thicker wafer.
    - a1369209993 4y ago
      > You can't get more transistors by using a thicker wafer. Well, you technically can, but it's not starting with a thicker wafer, it's growing a second (or more) layer of dopable silicon on top of the normal doped silicon/transistor gate insulator/wiring/more wiring/even more wiring stack of the chip, then adding another full stack on that new dopable surface. Pretty sure the fabrication infrastructure for that makes conventional, GDP-of-a-small-country photolithography fabs look cheap by comparison, though. Plus you'd be at least squaring (and probably much worse) the already not very good production yield.
ChuckMcM 4y ago
It is hard to imagine the scale of these things, I know if you had tapped me on the shoulder at Intel in the 80's and said, "in 40 years, the chip your looking at will fit in a couple of square mm of silicon." I would not have believed you. Of course it doesn't "really" fit in that small a slice as you need to get the signals into and out of it and those points take space, but it is doesn't take much space.
- eigenvalue 4y ago
  But didn't you intellectually know that this would be the implication of Moore's law if it could actually hold over such a long period? Maybe it's more a manifestation of how counterintuitive exponential growth is to human sensibilities.
  - ChuckMcM 4y ago
    To be fair I took way too much math to be comfortable in my college days but when at Intel everyone (even Gordon) knew that "Moore's Law" wasn't a "law" (like the Law of Gravity) it was an observation on the current state of the art. As a result everyone made the assumption that semiconductor scaling was an S curve and we happened to be in the exponential part of that curve but it would taper off. And everyone in the design engineering team felt it would taper off way sooner than it has!
    - aswanson 4y ago
      Was it common knowledge back then that CMOS would eventually deprecate TTL, ECL, etc?
      - ChuckMcM 4y ago
        Yes. Process changes, transistor geometry, dielectric materials, were all things that people expected to change. That customers would stop using TTL was pretty avant-garde, but when ASICS became "affordable" (basically custom chips for non-chip companies) it was obvious that volume manufacturers would condense a bunch of TTL into a single package just for cost reasons. But fundamentally electrons and 'charge' are quantum in nature and even in the 80's if you're transistors were "too close" you could get electron tunneling between them. So I, and others, assumed there was a really hard limit on how small you could go (and it was likely above 100nm rather than below it). And of course now hardly anyone used old 90nm tech, I think 40nm is the current "jelly bean" process but I freely admit I've not looked at the geometries used in the vast Chinese IC market of "support" chips.
daniel-cussen 4y ago
So sad. Such a waste. Won't even make it before the invasion. Trying to be valuable for a worthless president-elect of America. It is not 3 nanometers according the Metric System anyway. Oh well. Mainland flags on the Taiwanese monuments. How many months away, let me check my predictions, I think 70 days or so, give or take 15. Shit getting real hot real fast.
squarefoot 4y ago
What about the rest? I mean, how is other less advanced but still important chips scarcity addressed? Their production was hit as well.
monksy 4y ago
Biggest question here I think is the geopolitical things about this: Where will this be developed? My understanding is that the only fabs this is possible is within Taiwan. That's a massive issue with the current posturing of war.
- nlop 4y ago
cloudengineer94 4y ago
Can't wait to see a M2 Pro with 3nm. Looking forward to get 12-15h battery life on a 14" MBP.

393 points by carlycue 4y ago

Kye 4y ago

It's hard to remember looking at such tiny marginal improvements that they do compound over successive generations. "Only" a few percent is the difference between the Apollo computers and being able to simulate them with Redstone in Minecraft on a consumer computer over the gap of time that separates them.

sho_hn 4y ago
Can we herald Minecraft-Redstone as the new universal virtual machine that does what WASM couldn't?
- Kye 4y ago
  Give it time. Someone will make the JRE run on WASM and wipe away the distinction.
  - jeroenhd 4y ago
    > Someone will make the JRE run on WASM https://teavm.org/ https://teavm.org/ Minecraft contains some native dependencies, though; you'll need something like https://copy.sh/v86/ https://copy.sh/v86/ or https://bellard.org/jslinux/ https://bellard.org/jslinux/ with the right operating system image to run it in browser.
- muttled 4y ago
  Can't wait for my machine to come to a crawl as I walk up to some machine the size of a city and find out it's actually mining crypto

klxmarket 4y ago

Does anyone have rumors/insider knowledge about the progression of Epyc/Threadripper? Threadripper seems insanely expensive right now, will the next generation be faster at least or use less energy? Or, in other words, does it make sense to wait?

gjsman-1000 4y ago
Threadripper appears to be basically dead for most markets, being slowly cannibalized by the standard Ryzen platform.
- bryanlarsen 4y ago
  Cannibalized from the bottom by Ryzen and from the top by Epyc (aka Threadripper Pro).
zitterbewegung 4y ago
Threadripper pro is going to be the only workstation that makes sense anymore. Consumer threadrippers are being phased out. This is all public knowledge . You are better off with high end Ryzen now .
freemint 4y ago
Almost all Threadripper capable silicon ends up in Epyc. Once AMDs server market share is saturated Threadripper will come back. The reason why Intel is looking to push new HEDT is because their server market share is decreasing.
ptomato 4y ago
Threadripper is pretty reasonably priced; a 5995WX is about $101/core, or about 3% more than a Epyc 7773x for 10% more performance. For comparison, a Xeon Platinum 8380, which has roughly similar perf per core, costs $224/core. Sure, consumer CPUs are a bit cheaper; i9-12900kf is about $45/core (though half of those are slow cores) and 5950X is about $34/core, but price discrimination for server lines has always been fairly standard. I think the least expensive you can get into Epyc Milan is around $55/core, but that's on a part that only needs half the cores on an 8-core chiplet to be functional; the 7773x needs all of them, for 8 chiplets, and the 5995WX is that but with even tighter binning for higher clocks.
trynumber9 4y ago
Genoa, from which the next generation TR will likely derive, is up to 96 cores in 12 N5 chiplets with a new N6 IO chiplet that supports PCIe5 and 12 channel DDR5. It has some added instructions (AVX512) and will likely be more efficient at the same clock rate but they will be pushing the clocks higher instead. I would not wait around unless you have plenty of time. I doubt a cut down Genoa will show up on workstations until the server market is satiated.

hardware2win 4y ago

Why do we waste state of art, bleeding edge CPUs manufacture capabilities on some telephones? Who needs phones this fast?

colinmhayes 4y ago
Because 95% of people think their computers are fast enough but want more battery life on their phone I suppose.
- TheMode 4y ago
  Until you discover that any new performance/efficiency discovery gets spent on more bloated software.
- hardware2win 4y ago
  My random ass phone survives something like a few days of random usage Do we need more?
  - JshWright 4y ago
    Have you considered that your usage pattern may be atypical?
    - hardware2win 4y ago
      Yes, but I dont believe that theres this many phone addicted ppl
      - sho_hn 4y ago
        You don't have to be phone-addicted for your phone usage to keep going up. In a lot of societies ever more daily tasks continue to migrate off PC and onto phone apps. The number of services you interact with primarily through your phone (say, booking a hairdresser appointment or getting notified your dry-cleaning is done) keep going up everywhere. People use their phone for contactless NFC payments, for public transit check-in/check-out, etc. Having enough charge to last the day becomes increasingly not optional. Everyone gets habituated by context to look at the thing more and more as the gateway to everything.

bogomipz 4y ago

I had a question. I apologize if this a bit naive. The first slide shows the N3 releases go though 2025 and then we see the arrival of N2. How significant are these numbers in regards to end of Moore's law? Will we saw N1 in the next 10 years or is that getting to a process that requires something radically new like carbon nanotubes etc?

arroz 4y ago
Idk if Moore’s law is still in effect as stated It isn’t actually a law, it is more of an observation / prediction But people have been inventing new technologies to be able to still improve chips (for instance, finfets and now GAA)
mastax 4y ago
Completely insignificant. They're just names. Intel is going "Intel 4" -> "Intel 3" -> "Intel 20A". Everyone will call them 4nm, 3nm, 20Å (Angstrom) despite them explicitly not being that, but it's a hard industry habit to break.
mastax 4y ago
I'll also mention that we should have reasonable node progress through 2030 at least. There's plenty of room at the bottom with just EUV multi-patterning and a few other very practical improvements. Beyond that I'm less hopeful but I wouldn't bet against it.
TooKool4This 4y ago
I think this is not the correct way of thinking of Moore's law. Like mentioned elsewhere, Moore's law is not so much a law as a self-fulfilling prediction. Semiconductor companies follow Moore's law (or recently an approximation) to stay competitive because their competitors do it and hence Moore's law continues. The cost of not marching along to Moore's law can mean you will get left in the dust (see Intel). I think a better question to ask is whether the underlying economic factors behind continuous process tech improvements are healthy. Is there enough value-add to the final user by continuous process tech improvements? Are the costs for that improved process tech scaling with the value-add? And is the competitive landscape healthy? While that holds true, companies will keep looking for process tech improvements to give them a competitive edge. In the 80-90s this was very much true but in recent decades it was to a lesser extent hence why we see consolidation/reduction in the number of foundries, foundry services to amortize the cost of older node-tech, and R&D going to companies/partnerships that can capture the most end user value-add (Apple/TSMC). Looking forward I think the economics are very healthy with a design-house/foundry service model that we have right now so I would guess that Moore's law (or some approximation) will continue for the next decade. There are a lot of process tech innovation that can lead to better performance that are not necessarily scaling related. In fact, scaling transistors stopped being very useful a while back afaik due to the breakdown of Dennard's scaling.

pvsukale3 4y ago

Can someone who is into chips explain how big of a thing this is? And what maybe next?

ksec 4y ago
>And what maybe next? N2 in 2025. N1.4 or may be N14A in 2027. Roughly N1 in 2030. I believe we will hit an economic wall by the end of this decade. i.e The cost of Next Gen node exceed what the market are willing to pay for it.
adam_arthur 4y ago
The biggest gains in performance and efficiency almost always come from moving to newer gen manufacturing. So pretty big deal for computing. We may be close to the age where most laptops are fanless, for example. Most non apple devices still on 7-11nm equivalents since apple gets first dibs on new gen fabs from TSMC (pay for the right)
- drexlspivey 4y ago
  > We may be close to the age where most laptops are fanless, for example. Correct me if I’m wrong but high performance fanless laptops are only possible with ARM chips atm. Has any other big laptop chip designer even announced plans for anything remotely close to M1/M2?
  - adam_arthur 4y ago
    Most efficiency gains come from manufacturing fab process, not whether it's ARM or x86. M1 is the only 5nm processor on the market right now. Yes, you will see quite comparable performance once Intel and AMD get to 5nm as well
    - jasonwatkinspdx 4y ago
      Architecture does still matter. M1's decoder is 8 issue. You just can't build that for x86 without pipeline depth or some other resulting tradeoff making it pointless.

nicolaslem 4y ago

From the outside, having Apple securing the latest and greatest nodes for so long feels kind of anti-competitive. Apple has been selling phones and laptops with N5 for two years and I don't think we still have any competing product in the hands of consumers using N5 yet. If I'm not mistaken Nvidia and AMD are about to release products using N5.

klelatti 4y ago
We probably have 3nm production on this timescale because of the long term relationship between Apple and TSMC and the $100bn + that Apple have spent with TSMC over that time period. No one else has done this. Apple pays the money and takes the risks, so they get the rewards.
- ohgodplsno 4y ago
  "Takes the risks" Takes what risks ? Buying the riskless new transistors that TSMC puts out because they know that they work ? Apple taking risks would be making the chips themselves (see: the failure that was itanium and how it screwed Intel because they had to reorganize their facilities for it), not buying it wholesale and just having TSMC print it.
  - klelatti 4y ago
    The risk that TSMC doesn't deliver on node improvements / deliver the relevant SoCs in the required numbers. And if you think that risk is small / nil I would point you to Intel's recent track record. And just to point out that Apple actually does bear the risk you've highlighted as Itanium was a design (which Apple does) not a manufacturing failure.
    - lotsofpulp 4y ago
      There is also risk that sufficient consumers do not want to buy Apple’s products at a sufficient price premium to offset the price premium that Apple paid to TSMC.

alberth 4y ago

Seems like this missed Apple's M2 / iPhone 14 release by a few months.

bee_rider 4y ago
I think the it must be more outside the window than the release dates make it seem -- Apple must, I guess, do some QA and build up a decent stockpile before the release of a new iPhone.
bongobingo1 4y ago
Luckily it will be around for the M3 and iPhone 15... and the M4 and 16... and ... The lead time would be enough, that I doubt M2 was ever going to be a 3nm chip.
- jamiek88 4y ago
  I read that it was. The M2 was backported to the N5 process due to pandemic delays. I can’t actually find anything other than ‘analyst states’ type links though.
Slartie 4y ago
It's not like they have 3nm chips ready the day after production. When they "begin production", it takes months until the first actual, working chip from that production leaves the fab. And then it's not like the day after, Apple could produce iPhones or Macs with those chips. It takes months from having the first chip in hand until production churns out volumes of finished devices.
- wtallis 4y ago
  This article is specifically about the high-volume manufacturing milestone, which can be over a year after the first working chips leave the fab.
whynotminot 4y ago
Unfortunate. That will be three straight iPhones on essentially the same node, which I think hasn't happened yet. Might also lead to some awkwardness for Apple in having to port a design running on an older node to a newer one, if M3 does use 3nm. By all accounts, and if the pattern holds true, the M[n] chip is generally the scaled up version of the latest A series design. So if we have a release of A15 on 5nm, and the M3 is going to be based off that design, but ported to 3nm, that's kind of an interesting situation.

syntaxing 4y ago

Pardon my ignorance on this subject, but at 3 nm, don’t you get into some weird quantum artifacts because the layers are so stupidly close? Curious how that is addressed?

coolspot 4y ago
Not “layers”, but “features”. 3nm is basically a pixel size for chip schematics, it doesn’t mean that they draw 1px features with it.
- samstave 4y ago
  This was always my understanding is that the litho(?) mechanism can "print" in 3nm resolution, which allows the overal scaling of all features to be based on this "pixel" resolution. I was dumbfounded when even hearing about 14NM YEARS before it was a thing (I also got to see 64-core concepts at intel in ~1999 or so) 3nm is mind boggling amazing. Whatever happened to "voxels" (before the graphics term, intel was creating "voxels" that were used to use light to transfer vertically between layers... but I stopped following CPU arch years ago.
  - agar 4y ago
    hah, I remember when "submicron technology" was the bleeding edge of chip design. :-) https://cordis.europa.eu/project/id/554 https://cordis.europa.eu/project/id/554
- ajross 4y ago
  It's not even that. Nothing in a modern process node is as small as the node size, and in fact with modern processes it's not even close. I just checked, and per some reference on wikipedia TSMC 3nm's metal pitch is expected to be 24nm (so, ~12nm wide metal "wires" on the lowest level of interconnect are the smallest things you'll see on a picture). What's been happening is that fabs have been exploiting more and more tricks to increase transistor density while still using the larger feature sizes. So flat transistors became finfet's, increasing their gate area and allowing chips to use fewer of them for the same silicon area, etc... So read "3nm" as "a process with the same transistor density as you would expect had some ancestral ~90nm process been shrunk by a factor of 30".

Kukumber 4y ago

They are 1 innovation away to become in a position with no way to compete The knowledge and education backlog is way too high for the West Scary times

api 4y ago
Hey but we maximized shareholder value.
upupandup 4y ago
meh Samsung already started 3nm chip production last month and they are not facing an imminent invasion https://www.theverge.com/2022/6/30/23189362/samsung-3nm-chips https://www.theverge.com/2022/6/30/23189362/samsung-3nm-chip...
- Kukumber 4y ago
  "invasion"? what do you mean exactly? you meant reunification? i don't see how that could be a problem, we do business with China already, it would just become one of their state, you can still trade with them Or you meant as a result the US would not be able to steal the fabs, tech and workforce? (and by steal i mean purchase, just like we write about how China is stealing our tech when they purchase patents or by other deep internal means) Samsung is in a worse position than intel, not only it is Korean, and they have problems with their northern neighbor, as well as with Japan, but they also got hit by the anti-competitive behavior and trade war from the US, and were told to stop development of their in-house chip (Exynos), to place Qualcomm as a western leader, despite their poor tech https://old.reddit.com/r/Android/comments/71rjyx/why_exynos_is_not_used_by_samsung_in_the_us/ https://old.reddit.com/r/Android/comments/71rjyx/why_exynos_... And i'm not sure if The Verge is a trustable source, they either have insider knowledge or their source is manipulative, because that contradicts with the Exynos story If what they claim is true, then that'll be interesting to see if their "promise" can become a reality, time will tell But as a matter of fact, still nothing is happening in the west, and that was my entire point
  - wing-_-nuts 4y ago

eis 4y ago

So I wonder if the M2 Pro/Max/Ultra will after all be on the N3 node. If N3 HVM starts next month, the A15 being on N5P and it being a year until the A16 on N3 will be released and Apple being the first to use N3... some other Apple silicon needs to use the capacity first, or am I missing something?

BoardsOfCanada 4y ago
All I've heard is that they (M2 pro+) will all be on the N3 node, which would indicate release in the first months of next year.
msbarnett 4y ago
All of the M1/Pro/Max/Ultra shared the same fundamental core design. Presumably the same will be true of the M2 series. As someone else here said, fab nodes are more like Lego blocks than a printer’s dpi – moving a design to a new node means rebuilding it in terms of the new node’s building blocks, not just “shrinking the design”. So if the M2 Pro/Max/Ultra are intended to follow the same “reuse the cores (possibly rearranged) with more GPU blocks/cache etc” it seems unlikely. But if the make a design break within the M2 series then it’s possible? I’d expect Apple to follow their historical behavior and lead with the next A-series phone processor on the new node first. M1 Pro/Max/Ultra chips have huge surface areas – since process defect rates are driven down over time, it makes sense to start with your smallest chips first, so that you can get good yield out of your big chips once the defect rate is lower.
- adam_arthur 4y ago
  Intel famously followed the "tick-tock" model where they would alternate between designing a new architecture and then moving that architecture to a new processing node. So not sure it's true that you can't shrink down a largely similar architecture from one process to another. Obviously it's fallen off the wagon a bit here, but seems more due to operational issues at Intel than it being fundamentally not doable https://en.wikipedia.org/wiki/Tick%E2%80%93tock_model https://en.wikipedia.org/wiki/Tick%E2%80%93tock_model

unixhero 4y ago

Are these the same 3nm as Intel operates with? Or are we seeing nano-meter inflation again, in such a way we did with Gigahertz...?

trynumber9 4y ago
Gigahertz are still the number of cycles. That didn't inflate, it correlates to a real timing. TSMC call it N3 instead of 3nm for a reason. It's not 3nm.
- zerocrates 4y ago
  Gigahertz weren't inflated per se, but there were similar effects to the name games with process nodes with clockspeeds when those were more directly seen as indicators of performance. I'm thinking particularly of AMD having Athlon model numbers that were 1:1 to clockspeeds for years, then Athlon XP switching to ones that were above their actual speeds, to sort of vaguely indicate which Intel clockspeed they were claiming performance parity with. Of course once they were beyond the clockspeed-above-all Pentium 4, Intel themselves stopped focusing on marketing clockspeeds and things gave way to basically arbitrary naming/numbering schemes. (Or to some extent, core counts.)
  - 0x457 4y ago
    Well, performance is roughly = clock speed * instructions per cycle. When intel was dominant (pre-Anthlon XP and pre-Core era), Clock speed alone could have been used to measure performance. Then, AMD Athlon XP come out with higher IPC than Pentiums, but the customers were used "Higher clock, higher performance" even though Athlon XP was faster at the same clock speed. So, they've changed model names to indicate performance parity, that was the game intel played. They didn't lie or mislead about clock speeds anywhere.
    - zerocrates 4y ago
      That's my point: this seems to me more less exactly where we are now with "Intel 7" being their "10 nm but better-er" process and the previously-known-as-7nm becoming "Intel 4." They're saying, well, the actual nanometer number has long been a little wishy-washy anyway, so we're jettisoning the pretense that this is a measurement of anything in particular and just picking a number that sounds better and aligns with our competition's numbers. And of course it's not just Intel marketing this way, everyone does, but their more recent naming change makes it more transparent. Tired of years of saying "welll, TSMC's Xnm (or X number with no units that's sort of implied to be nm) is really equivalent to our X+Ynm," they just go for marketing on parity. Like I said in the start of my previous post, this isn't actually inflating (or deflating as the case may be) but it's just taking a concept that's widespread among the consumers as a proxy for quality/value and marketing to that idea rather than any actual physical characteristic.

deleted 4y ago

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sylware 4y ago

china invasion too?

marcodiego 4y ago

If any chip manufacturer can hear me: please, change this metric to transistor per square millimeter. Thanks!

szatkus 4y ago
That wouldn't work. Transistors density depends on what you're going to build. And there are other variations between processes.
wtmt 4y ago
Do you mean transistors per cubic millimeter? Cubic centimeter (cc) may be a better choice since it’s already a more common measure of volume at smaller scales for most of the world.
- wtallis 4y ago
  Areal density rather than volumetric density will continue to be the most relevant basis for comparison as long as chips are still being fabricated on wafers with a fixed total area. Flash memory has been 3D for years but the important density measurement correlated to cost is still Gbit/mm^2.
- IshKebab 4y ago
  No, cubic mm makes no sense because transistors are created on the surface of the wafer. It's surface area that matters. You can't get more transistors by using a thicker wafer.
  - a1369209993 4y ago
    > You can't get more transistors by using a thicker wafer. Well, you technically can, but it's not starting with a thicker wafer, it's growing a second (or more) layer of dopable silicon on top of the normal doped silicon/transistor gate insulator/wiring/more wiring/even more wiring stack of the chip, then adding another full stack on that new dopable surface. Pretty sure the fabrication infrastructure for that makes conventional, GDP-of-a-small-country photolithography fabs look cheap by comparison, though. Plus you'd be at least squaring (and probably much worse) the already not very good production yield.

ChuckMcM 4y ago

It is hard to imagine the scale of these things, I know if you had tapped me on the shoulder at Intel in the 80's and said, "in 40 years, the chip your looking at will fit in a couple of square mm of silicon." I would not have believed you. Of course it doesn't "really" fit in that small a slice as you need to get the signals into and out of it and those points take space, but it is doesn't take much space.

eigenvalue 4y ago
But didn't you intellectually know that this would be the implication of Moore's law if it could actually hold over such a long period? Maybe it's more a manifestation of how counterintuitive exponential growth is to human sensibilities.
- ChuckMcM 4y ago
  To be fair I took way too much math to be comfortable in my college days but when at Intel everyone (even Gordon) knew that "Moore's Law" wasn't a "law" (like the Law of Gravity) it was an observation on the current state of the art. As a result everyone made the assumption that semiconductor scaling was an S curve and we happened to be in the exponential part of that curve but it would taper off. And everyone in the design engineering team felt it would taper off way sooner than it has!
  - aswanson 4y ago
    Was it common knowledge back then that CMOS would eventually deprecate TTL, ECL, etc?
    - ChuckMcM 4y ago
      Yes. Process changes, transistor geometry, dielectric materials, were all things that people expected to change. That customers would stop using TTL was pretty avant-garde, but when ASICS became "affordable" (basically custom chips for non-chip companies) it was obvious that volume manufacturers would condense a bunch of TTL into a single package just for cost reasons. But fundamentally electrons and 'charge' are quantum in nature and even in the 80's if you're transistors were "too close" you could get electron tunneling between them. So I, and others, assumed there was a really hard limit on how small you could go (and it was likely above 100nm rather than below it). And of course now hardly anyone used old 90nm tech, I think 40nm is the current "jelly bean" process but I freely admit I've not looked at the geometries used in the vast Chinese IC market of "support" chips.

daniel-cussen 4y ago

So sad. Such a waste. Won't even make it before the invasion. Trying to be valuable for a worthless president-elect of America. It is not 3 nanometers according the Metric System anyway. Oh well. Mainland flags on the Taiwanese monuments. How many months away, let me check my predictions, I think 70 days or so, give or take 15. Shit getting real hot real fast.

squarefoot 4y ago

What about the rest? I mean, how is other less advanced but still important chips scarcity addressed? Their production was hit as well.

monksy 4y ago

Biggest question here I think is the geopolitical things about this: Where will this be developed? My understanding is that the only fabs this is possible is within Taiwan. That's a massive issue with the current posturing of war.

nlop 4y ago

cloudengineer94 4y ago

Can't wait to see a M2 Pro with 3nm. Looking forward to get 12-15h battery life on a 14" MBP.