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Why is Apple's M1 chip so fast?
- socialdemocrat 6y agoWhat are the technical reasons why the M1 chip is so fast. Does Apple use any exotic tricks? Can Intel and AMD do the same trick in their chips?
- jonplackett 6y agoread the article!
- Justsignedup 6y agoSounds like apple made multiple specialized processors for specific tasks, built a motherboard around that, and cooked all that into the OS. It's a bit of a cheat since they aren't building a generic computer architecture, but a very very specialized one. This is different with say Windows architecture. In windows vendors work on generic cpus/gpus/motherboards. Some hardware isn't exactly available or uniformally accessible due to drivers and such. This is kind of the huge benefit Apple has by creating the hardware, OS, drivers, languages and libraries.
- zepto 6y agoThis is what they do with everything. It is the reason for vertical integration. Calling it ‘a cheat’ is somewhat weird. The point is that a general purpose CPU is a bad solution for a personal computer. The neural engine is about processing the ambiguous world that humans occupy so that the human doesn’t have to translate so much for the computer. The GPU is about communicating visually with humans.
- reallydontask 6y agoGP said a bit of a cheat not that it was cheating. Point is that if you try to run a different OS, it will likely run slower, perhaps significantly slower than running macOS
- zepto 6y agoGiven that the individual cores benchmark at the very high end of any core available today, this is almost certainly not significant. If another OS doesn’t take advantage of the specialized processors, it will run slower, but only on specialized loads.
- bee_rider 6y agoAnecdotally, I saw some folks on reddit's linux board that were running Linux in virtual machines on the M1 and getting quite decent results.
- eng2prog 6y agoI see Apple following the path of Nintendo. They don't need to compete on performance, their users aren't buying for performance. Vertical integration puts you at tremendous risk of falling behind. The future is keeping Apple "fresh", "cool", etc... While keeping product costs low to compensate for a falling market share. Really says something that Apple is willing to compromise on long term hardware performance.
- zepto 6y agoCan you explain how they are ‘compromising on long term performance’? I don’t see any logic that supports this claim.
- jitl 6y agoHow are they following the Nintendo path? These machines are clearly faster than the market segment, and apple is the leader in ARM CPU technology at this point, and they’ve been the mobile CPU leader for about 7 years, whereas Nintendo’s latest offering integrated mostly commodity technology from Nvidia Tegra. I don’t see how you can draw this parallel.
- ascagnel_ 6y agoNintendo has, since the Wii, shied away from bleeding-edge or custom components, preferring to use cheaper, proven tech that they can more easily maintain but is still strong enough for their needs. Just look at the Switch -- it uses the Tegra X1 in a device that launched in March of 2017, despite the X2 having been available for more than a year. Apple, on the other hand, has been running rings around Qualcomm and other ARM vendors for a while now, and sharing tech makes it all the more important that they continue to be competitive.
- danbolt 6y agoI think only really the SNES/N64 years embodied the cutting-edge solutions associated with novel games. Their whole ethos to entertainment (especially the handheld line becoming the core product in a way) still feels embodied in Yokoi's "lateral thinking with seasoned technology" philosophy.
- eng2prog 6y agoToday all of this is exciting, but I have a bad feeling this is going to slide Apple towards a low performance future. They Apple'd themselves and locked themselves in. In 2 years, secrets aside, Apple would need to beat all 3 big dogs to be the top. How long can they sustain that?
- vb6sp6 6y agoCouldn't they could just switch back then?
- eng2prog 6y agoThey could at significant expense. But why would they? The users don't buy for performance.
- vb6sp6 6y agoBasically every laptop from here on out is going to be benchmarked against these devices. And battery life seems to be the sleeper performance metric here. Every review is going to be "you could get 6+ more hours if you just bought the macbook"
- deleted 6y ago[deleted]
- rado 6y agoToday they overdelivered, why is it then so hard to believe they'll meet the expectations of a scaled up SoC? It's guaranteed.
- zepto 6y agoHow do you reach this conclusion? Their individual cores and memory architecture still beat almost everyone else on general purpose loads without any of the specialized engines.
- mrkstu 6y agoThey've been sustaining it for many years already, that's how they've gotten to the point of being able to passing up the incumbents. They didn't just start on this path this year, its the culmination of a long play strategy.
- sliken 6y agoApple did optimize for some common use cases, reference counting (as used by objc++), javascript tweaks, and for emulation for rosetta2. However they also made a great general purpose CPU that will run many standard codes impressively quickly for impressively little power.
- NobodyNada 6y agoIf that were the case, though, we would expect to see performance gains only in areas the M1 is specialized for -- but that's not what we see. The M1's GeekBench scores are impressively high, and general-computing workloads like compiling code are very fast as well, indicating that the M1 is fast in general, not just for specific tasks. There's been a lot of hype about things like "specialized hardware for NSObjects," but AFAIK that's more of a flawed/outdated design on Intel' side than a specialization on Apple's: the "magic" is really just ARM's weaker & more modern memory consistency model, which makes things like reference counting substantially faster.
- socialdemocrat 6y agoYeah and I think it will be quite interesting to see in the years ahead how this kind of highly specialized approach to computing will stack up against the more generic wintel approach, and how customers will respond. Customers may end up with having the choice between a very high performance system at competitive prices, vs an open architecture which has more flexibility in what you add, but which will ultimately cost more and have worse performance. You can see this play out in different markets. Just look at Tesla e.g. They are taking the Apple approach to car making with full vertical integration. They are doing everything from making their own alloys to creating their own machine learning hardware. I think we are at some kind of paradigm shift and the old guard has been caught off guard.
- stefan_ 6y agoThey use this one trick that AMD and others hate: they paid TSMC to use up all of their 5nm capacity.
- GloriousKoji 6y agoI have an anecdote possibly related to this. I work for a semiconductor company and we were in pretty good standing with TSMC. All of a sudden we were informed we should longer contact the usual engineers them and a new team of engineers was assigned to us. It was very clear the new staff was their B-team. Rumor around the office the A-team went to support Apple.
- macintux 6y agoThe word I learned in years past because of Apple that applies to it in several ways is "monopsony": the ability to control the market for a product by being the dominant buyer of same.
- lotsofpulp 6y agoThat is not what monopsony means. Monopsony means there is only one buyer. Apple is one of many buyers. However, they are able to secure the resources since they can pay the most.
- macintux 6y agoMonopsony means there’s a dominant buyer, not just a single buyer. Fortune was talking about it almost 10 years ago. https://macdailynews.com/2011/07/05/how-apple-became-a-monopsonist/ https://macdailynews.com/2011/07/05/how-apple-became-a-monop... Of course they’ve been accused in the Supreme Court of being a monopsonist with regard to the App Store, but that’s a separate discussion. (Update: regrettably my economic theory is weak, so while I think it makes sense to apply the term, after more reading I can't argue the case with a reasonable level of conviction. Certainly there should be some way to describe a buyer who locks up a supply of components to the exclusion of competitors, as Apple has done on multiple occasions dating at least to the original iPod hard drives.)
- amq 6y agoI see two main reasons: - 5nm process (1.8x the density of 7nm [1]) - unified memory directly on the SoC [1] https://hexus.net/tech/news/industry/130175-tsmc-5nm-will-improve-logic-density-18x-7nm/ https://hexus.net/tech/news/industry/130175-tsmc-5nm-will-im...
- kllrnohj 6y agoUnified memory is old, every CPU with an integrated GPU is on unified memory. It's not doing anything at all for M1's general performance. The main reason for M1's performance is just that Apple managed to get an 8-wide CPU to work & be fed. That's it. That's the entirety of the story of the M1. Apple got 8-wide to work, while Intel & AMD are still 4-wide. ARM's fixed length instructions are helping a ton there, but Apple also put in work to feed it. All the other shit about specialized units & unified memory & vertical integration is all irrelevant and mostly wrong. The existing Intel Macbook Airs are all unified memory with specialized hardware units for specialized tasks, too (Intel QuickSync is 9 years old now - dedicated silicon for the specialized task of video encoding). Apple did absolutely nothing new or interesting on that front. Other than marketing. They are magic at marketing. And also magic at making a super wide CPU front-end, with really good cache latency numbers.
- sliken 6y agoThat's overly simplified. Larger order buffer, larger caches, lower latency caches, more outstanding loads, etc. They also managed in a cheap platform (mac mini = $700) get 4266 Mhz memory working with about half the latency of any x86-64 I've seen. The mac mini can manage a random cacheline (assuming a relatively TLB friendly pattern) of around 30-33ns. Maybe the usual intel core i7/i9 or ryzen 5000 look rather quaint with their 60ns or higher memory latencies.
- kllrnohj 6y ago> They also managed in a cheap platform (mac mini = $700) get 4266 Mhz memory working with about half the latency of any x86-64 I've seen. The mac mini can manage a random cacheline (assuming a relatively TLB friendly pattern) of around 30-33ns. Where are you getting those numbers? From https://www.anandtech.com/show/16252/mac-mini-apple-m1-tested https://www.anandtech.com/show/16252/mac-mini-apple-m1-teste... "In terms of memory latency, we’re seeing a (rather expected) reduction compared to the A14, measuring 96ns at 128MB full random test depth, compared to 102ns on the A14." Which would put M1's DRAM latency at worse than a modern Intel or AMD desktop, which is measuring around 70-80ns: https://www.anandtech.com/show/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested/5 https://www.anandtech.com/show/16214/amd-zen-3-ryzen-deep-di...
- deleted 6y ago[deleted]
- jayd16 6y agoIs this a bot? This is just lifted from the article verbatim. Do I get my Turing tester badge?
- chess_buster 6y agoDid you read the article? Does not seem like it.
- gfody 6y agoIIRC Apple got some exotic automated optimization tech when when they acquired PA Semi - I think it was mentioned in the Steve Jobs biography. The A chips have always been impressive and the timing lines up.
- wiremine 6y agoI keep coming back to the implications for the rest of the industry: 1. What does this mean for x86? 2. What does the answer to question #1 mean for Windows and Microsoft? Are they going to sit by and let Apple lap them? 3. What does the answer to question #2 mean for cloud computing? AWS is already making ARM chips... does the M1 change anything fundamentally about where the cloud goes with ARM?
- pishpash 6y ago#1: The writing's on the wall for x86, probably. Once its former monopoly rent is only justified by high-end "scientific computing" uses -- well you know what happened to IBM/DEC/SGI/HP and their workstation solutions...
- gtirloni 6y agoAt least for #2, see Windows ARM https://docs.microsoft.com/en-us/windows/arm/ https://docs.microsoft.com/en-us/windows/arm/
- __d 6y ago1. x86 (and then AMD64) has had vast amounts of R&D money and talent thrown at it for decades, with the result that it has out-performed every competitor: SPARC, MIPS, Alpha, PA-RISC, Itanium, etc. As a consequence of this domination, it has a massive software, tooling, and expertise advantage. But ... ARM, which through a series of coincidences, ended up being the right architecture at the right time for mobile devices, has had its own injection of talent and money, and has advanced rapidly in the last 15 years. The M1 is a long way from the ARM710 or StrongARM of the late 90's! Similarly, computer circuitry has evolved. Early minicomputers used small circuit boards with just a few gates to assemble their CPUs. In the early 80's, bigger CPUs were built from multiple "bit slice" chips ganged together. The modern PC motherboard has been a thing since the era of the Apple ][, growing through 8, 16, 32 and now 64 CPUs with ever-increasing speed and power, but maintaining a model of a motherboard and expansion cards. SoCs have been a thing for embedded devices for some time now: the M1 is perhaps the first really high-profile "computer" to use this technique to integrate its major architectural components in one "chip" (package). I think it's inevitable that others will follow, given the obvious performance and power gains to be had. AMD and Intel do this to some extend already. The AMD chips powering the new Platstation and Xbox consoles are SoCs, and Intel has sold embedded variants of its CPUs that are basically SoCs for some years now too. x86 has a long future ahead of it, but for the first time since Alpha (?) it's seeing a major competitor. Unlike DEC though, ARM has a broad and deep ecosystem behind it, and (as the article points out) there are some advantages to the instruction set that x86-64 will perhaps struggle to overcome. 2. Microsoft already has the Surface. They've known for some time that Apple's integration of hardware and software is hard to beat, and that the iPhone represented a technology that could be applied to laptops and desktops any time Apple wanted to do so. So ... they've already made steps in the direction of competing, but they have a lot of business-model challenges to overcome in order to do so. Honestly, I'd be much more interested in the futures of Dell, HP(E), Lenovo, etc, than Microsoft. This is a massive challenge for them. 3. No. The cloud vendors are already moving towards ARM for power reasons. The AWS Nitro board is begging to be integrated with a Gravitron -- I would be surprised if Amazon doesn't come up with a compute platform that's powered by a similarly integrated SoC in the very near future. The M1 helps accelerate this process because all Open Source software will now have to treat AARCH64 as a first-class citizen (which, to be fair, the Raspberry Pi has already helped to do). Similarly, commercial software vendors now have another market that will need a native ARM version in 2 years (after Rosetta2 is phased out, like Rosetta was for PPC). So .. I don't think it's changed the cloud direction at all, but it could make the transition faster.
- aey 6y agoBecause of the 12MB L2 cache as the point of unification. 865 snapdragon has a 4mb L3. Same as my recent intel MacBook. Apple can use at least as much more die as amd/qcom/intel’s profit margin.
- periya 6y agoAlso being on TSMC5 on top of significant micro architecture improvements ; ~630 instruction deep ROB, ability to queue ~150 outstanding load instruction and ~100 outstanding stores and huge TLBs which reduces swapping the anandtech article does a great job going into explaining this.
- aey 6y agoAll that helps, but if you look at the die you are going to see a massive 12MB L2 with a bunch of routing to all the L1s. That’s where the majority of the cost is going vs any other chip.
- bee_rider 6y agoIntel probably should have dropped their profit margin just to prevent this embarrassment. This is the foot in the door. Or through the door.
- kllrnohj 6y agoIf cache size was the answer then Intel would have already stuck more on their CPUs, and AMD's 32MB on Zen3 would be carrying far more weight against the M1 than it is. Bigger caches mean higher latency caches, it's not strictly a matter of bigger is better.
- aey 6y agoIt’s an L2, amd zen has 2x16mb L3s, with a wacky point of unification. L3 is muuuuch slower than L2. Apple’s L2 is huge and is the PoU for all the cores. I wouldn’t be surprised if it has direct routing to all the L1s since they are so small. 5nm doesn’t hurt.
- hardwaregeek 6y agoUgh. Any way around the requirement to sign in with Google? Very frustrating that this is required to read a damn blog post.
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- ducttapecrown 6y agoUsing a JavaScript toggle button also works.
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- jonplackett 6y agoI'm never sure if I like or hate when a site's adblock/article limit/sign in requirement etc is so easy to circumvent. On the one hand it's good for me, on the other I feel like, couldn't you have put in a bit more effort? if you're going to make it that easy why bother? (I know it's just because most people don't realise)
- jmnicolas 6y agoI use uBlock origin. Never saw any signing form.
- nathanasmith 6y agoI use the excellent Readium bookmarklet[0]. Drag it to your bookmarks bar and whenever you encounter a Medium article you can't read, just click it and problem solved. [0]https://sugoidesune.github.io/readium/ https://sugoidesune.github.io/readium/
- addaon 6y agoMy recollection is that when P. A. Semi was acquired by Apple, a major part of their "secret sauce" was a custom cell library. And then Intrinsity, a few years later, also seemed to be using custom cells on Samsung's process. Is this recollection / understanding correct? Is Apple still using custom cell libraries rather than TSMC's standard library?
- ahupp 6y agoWhat does "cell" mean in this context?
- robert_foss 6y agohttps://en.wikipedia.org/wiki/Standard_cell https://en.wikipedia.org/wiki/Standard_cell
- dreamcompiler 6y agoIt's one level of abstraction above the transistor level; in other words gates and sets of gates. Designing at the raw transistor level is tedious, time-consuming, and requires specialized knowledge of low-level electrical and physics characteristics. When you design with standard cells, you only have to think about the logic functionality. https://en.wikipedia.org/wiki/Standard_cell https://en.wikipedia.org/wiki/Standard_cell The parent's question is about whether Apple really did do some of the designing at the transistor level by designing their own cells, rather than using a standard library. This could give them an edge that ordinary users of the standard library wouldn't have.
- morganw 6y agohttps://en.wikipedia.org/wiki/Standard_cell#Library https://en.wikipedia.org/wiki/Standard_cell#Library "A standard cell library is a collection of low-level electronic logic functions such as AND, OR, INVERT, flip-flops, latches, and buffers. " I think SRAMs are also built of standard cells & there can be a lot of flexibility to improve on the fab's library, particularly with multiple ports for caches.
- Geee 6y ago
- minddeep 6y agoGreat explanation and also a good read on challenges Intel and AMD will face going forward. I am wondering if any of the windows / linux laptop makers will follow suit? Or will it be too hard to use the generic windows / linux and optimize it for custom built hardware?
- eng2prog 6y agoWhy bother? Computing is blazing fast already. Anything that is slow should use multi threading. There's a reason most computers compromise on the processor performance, we don't need it. Take that extra few hundred and give me more ram and a better video card.
- jonplackett 6y agoBecause battery life.
- eng2prog 6y agoSo it's not the speed like the title says? Lol
- f6v 6y agoIt’s obvious that those are related, isn’t it? I want to have a powerful laptop which I can carry around all day. Yet latest Intel ultrabooks either throttle or get hot and loud. So much energy just get wasted on generating heat, that’s why passively cooled m1 looks like a wonder.
- jonplackett 6y agoIt’s the subtext isn’t it. Apple went on and on about performance PER WATT. They could crank up the power and shorten the battery life any time they like.
- vmchale 6y agoHope so. I could happily use arm chips on mobile.
- benjaminl 6y agoUnlike what has been said on Twitter the answer to why the M1 is fast isn’t due to technical tricks, but due to Apple throwing a lot of hardware at the problem. The M1 is really wide (8 wide decode) and has a lot of execution units. It has a huge 630 deep reorder buffer to keep them all filled, multiple large caches and a lot of memory bandwidth. It is just a monster of a chip, well designed balanced and executed. BTW this isn’t really new. Apple has been making incremental progress year by year on these processor for their A-series chips. Just nobody believed those Geekbench benchmarks showing that in short benchmarks your phone could be faster than your laptop. Well turns out that given the right cooling solution those benchmarks were accurate. Anandtech has a wonderful deep dive into the processor architecture. https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive/2 https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de... Edit: I didn’t mean to disparage Apple or the M1 by saying that Apple threw hardware at the problem. That Apple was able to keep power low with such a wide chip is extremely impressive and speaks to how finely tuned the chip is. I was trying to say that Apple got the results they did the hard way by advancing every aspect of the chip.
- vmchale 6y ago> Just nobody believed those Geekbench benchmarks showing that in short benchmarks your phone could be faster than your laptop. I saw a paper on (I think?) SMT solvers on iPhone. Turned out to be faster than laptops, I kind of brushed over it as irrelevant at the time.
- FpUser 6y agoI did believe those benchmarks. I also knew that sustainable load at those speeds if not throttled down would just melt the thing so yes they were irrelevant.
- simonh 6y agoMaybe in practice at the time, but in hindsight they were actually a valid indication of the true performance capabilities of the architecture. It’s just that a phone has too little thermal capacity to sustain the workload.
- burnthrow 6y agoIs anybody here using one of these for serious development, and can comment on performance? On reddit there are some comments about anything Java-related being rather slow for instance.
- vmchale 6y agoI'm also curious. Phoronix added clash/GHC compiler benchmarks which is relevant to my interests.
- olliej 6y agoIf they're still not using a native JVM Java devs will be running Java under Rosetta. While rosetta can run code with JITs the performance is nowhere near AOT perf (for many reasons)
- thoughtsimple 6y agoYou can get M1 native Java JDK from Azul. https://www.azul.com/downloads/zulu-community/?package=jdk https://www.azul.com/downloads/zulu-community/?package=jdk
- my123 6y agoThere's a need to use a native Java runtime instead of one running on Rosetta (like what IntelliJ ships). Azul Zulu is one.
- seek3r 6y agoIt really depends on your workflow. Also see: https://news.ycombinator.com/item?id=25238608 https://news.ycombinator.com/item?id=25238608
- grey-area 6y agoDepending on your definition of serious (I'd say it's serious when people pay money for it), I'm doing that and am quite happy with it. I haven't tried building any Java code though, only Go and Swift. I'm seeing about 2x performance (eyeballing build times) of a recent Intel MBP for compiling a medium size Go codebase, running natively on arm64. The machine is noticeably faster than previous iterations for most tasks. I've made an effort to avoid emulated code though so am running a patched version of Go 1.16 and tools. Not all tools have officially supported native versions yet, but the performance is definitely there.
- ogre_codes 6y agoWhile the M1 is super impressive, I'm kind of wondering how scalable the performance increases they made here are. They moved high bandwidth RAM to be shared between the CPU & GPU, but they[1] can't just keep expanding the SoC[2] with ever larger amounts of RAM. At some point they will need external RAM in addition to the on chip RAM. Perhaps they will ship 32GB of onboard memory with external RAM being used as swap? This takes a bit away from the super-efficient design they have currently. Likewise, putting increasingly larger GPUs onto the SoC is going to be a big challenge for higher performance/ Pro setups. I think Apple really hit the sweet spot with the M1. I suspect the higher end chips will be faster than their Intel/ AMD counterparts, but they won't blow them out of the water the way the current MacBook Air/ MBP/ mini blow away the ~$700-2,000 PC market. [1] I updated the text here because I'd originally commented here about the price of RAM which is largely irrelevant to the actual limitations. [2] As has been pointed out below, the memory is not on the die with the CPU, but is in the same package. Leaving the text above intact.
- dragontamer 6y ago> Moving high bandwidth RAM Its just LPDDR4. HBM is a different thing. You can tell because HBM has 1024-bits bus per chip, but LPDDR4 is just 128-bits per chip. There's almost nothing special about the RAM, aside from it being locked to the chip and unable to be upgraded. It seems like the clockrate to the LPDDR4 is a bit higher than average, but its nothing extravagant. > How do they manage even larger amounts of RAM? Perhaps they will have external RAM in addition to the on chip RAM, with perhaps 32GB of onboard memory and the external RAM being used as swap? This takes a bit away from the super-efficient design they have currently. They COULD just support a DIMM stick like everyone else. But Apple doesn't want to do that strategy and prefers packaging the RAM and CPU together for higher prices. This isn't a 1024-bit bus (that requires 1024 wires, usually an interposer). This is just your standard 128-bit LPDDR4, maybe at a slightly higher clockrate than others for a slight advantage in memory. ------ In case of HBM2, you can't upgrade RAM beyond one-stack per 1024-bit bus. A GPU goes 4x wide with 4x 1024-bit busses to 4x different HBM2 stacks for a massive 4096-pin layout (!!!), that's 4096 wires connecting a GPU to individual HBM2 chips. Hypothetically, a future GPU might go 6-stacks or 8-stacks (8192-wires), but obviously running all those wires gets more-and-more complex the bigger you go. So in practice, GPUs seem to be ~4-stacks, and then you just buy a new GPU and run the entire GPU in parallel when you need more RAM. > > Moving high bandwidth RAM to be shared between the CPU & GPU That's not the advantage. When the L3 cache is connected between CPU and GPU, you gain a bandwidth edge in heterogenous systems. AMD / Intel have been connecting L3 caches to their iGPU solutions for over a decade now. CPU - to DDR4 - to GPU is very slow compared to CPU - to L3 cache - to GPU. Keeping the iGPU and CPU memory-cohesive is a nifty trick, but is kind of standard at this point.
- d33lio 6y agoIt'll be curious when they inevitably release the "M2" chip with higher memory capacity. If M2 has 32gb support I'll buy one immediately. For now, I'll be sticking to my "never buy gen 1 of any technology" rule. Right along side my, "use tech until it breaks" rule, however if you incentivize yourself to be a "power user" meeting the latter rule is far easier than the former ;) .
- stetrain 6y agoYou can see the gaps in the lineup that they have yet to fill, since the 4-port 13" Macbook Pro and high end Mac Mini are still being sold with Intel CPUs. Both of those machines need at least 32GB options to properly replace them. I would guess we see that support in an M1X with more cores and more Thunderbolt lanes next year as they work their way up the lineup.
- grecy 6y agoIt's a total guess, but I figure "M" is for "Mobile", and it will increment up in numbers like the A series has done in iphones/ipads Then we'll see some other letter (Maybe) "D1" for Desktop perhaps for the machines next up the list performance-wise (higher-end Mac Book Pros and minis and lower-end iMacs.) And finally we'll see "P1" for the pros, which is the iMac Pro and Mac Pro. The real beast, hoping for at least 128 cores. All of them will just go up in number as the years go on.
- joakleaf 6y agoDon't you think "M" is just for "Mac"?
- grecy 6y agoIt sure could be, but I'll be shocked if they have their current M1 in the $999 MacBookAir and something still called "M1(x)" in the Mac Pro that has 128+ cores and >128GB RAM, etc. etc. IMO, that's a totally different product, and it needs a different naming convention. But I'm just guessing.
- AnthonyMouse 6y agoThe explanation provided by the article is poor. It has very little to do with SoC or specialized instructions -- it's fast on general purpose code. The main reasons appear to be that it's a solid design, i.e. competitive with what x86-64 processors are offering, and on top of that has some specific characteristics that x86-64 processors don't currently have (but obviously could). It's built on TSMC 5nm, which is possibly the most power efficient process in the world right now. It's using memory which is faster than the DDR4 currently used by the competition. It's a big.LITTLE design, which is more power efficient, because you get strong single thread performance from the big cores and higher efficiency on threaded code from the little cores. It's not magic. It's engineering.
- westwing 6y agoThe article goes into what makes it fast on general purpose code in the bottom half. Mainly, it's the better out-of-order execution that is possible with a large ROB, and how this wouldn't work as well on X86. Your points don't explain why at 3Ghz this chip can outperform 5Ghz chips in single-threaded workloads. Using a 5nm process can give you more cores and less power usage, but it won't improve IPC. The DDR4 is faster than average, but you can get those kinds of speeds on enthusiast PCs and it doesn't make a big difference there.
- AnthonyMouse 6y ago> Your points don't explain why at 3Ghz this chip can outperform 5Ghz chips in single-threaded workloads. It's a trade off. Making it wider is the reason the IPC is higher, but it's also the reason it is a 3GHz chip instead of a 5GHz chip. The author's explanation of why x86 processors can't do this is also not especially compelling. The reason very wide processors are atypical is that common spaghetti code has poor instruction level parallelism -- the processor can't extract what isn't there, so there is a point at which higher clocks become the way to make bad code run faster. Interestingly, synthetic benchmarks are often less susceptible to this because the code is optimized to maximize ILP. It's a shame we still have so few real world benchmarks (mostly because the applications still haven't been ported). > The DDR4 is faster than average, but you can get those kinds of speeds on enthusiast PCs and it doesn't make a big difference there. It depends heavily on the task, but the difference in some cases is close to 40%: https://www.tomshardware.com/reviews/best-ram-speed,5951-6.html https://www.tomshardware.com/reviews/best-ram-speed,5951-6.h...
- ahupp 6y ago> But Apple has a crazy 8 decoders. Not only that but the ROB is something like 3x larger. You can basically hold 3x as many instructions. No other mainstream chip maker has that many decoders in their CPUs. Does this mean I'd expect to see better IPC (instructions per cycle) on these chips vs an x86, due to better memory parallelism?
- deleted 6y ago[deleted]
- jonplackett 6y agoYes that's that main reason the article gives that a 2.3ghz laptop chip is almost as fast as a 5ghz zen3 chip with a lot more cooling.
- areoform 6y agoAs I've written elsewhere and the article discusses in excellent detail, something that's missing in the conversation is a discussion of the custom application specific silicon over here, https://areoform.wordpress.com/2020/11/30/tanstaafl-apples-m1/ https://areoform.wordpress.com/2020/11/30/tanstaafl-apples-m... (on HN, https://news.ycombinator.com/item?id=25256025 https://news.ycombinator.com/item?id=25256025 ) I dislike linking to myself, but the take is long and it essentially points out that Apple themselves hint at Application Specific silicon in the M1 in their keynote, and when added with their acquisitions of ASIC specialists, it's not a long-take to say that comparing the M1 against most vanilla X86 processors isn't quite fair. It's a very different beast with its own tradeoffs. By colocating several different application specific processors under one roof and selling it as a CPU, Apple may have revitalized/invented something new. It's a bit like the iPhone - taking elements that were already there and catalyzing them into a new form. This new not-quite-a-CPU SoC likely has significant implications for the future of computing that should be discussed and detailed. Because, There Ain't No Such Thing As A Free Lunch.
- pram 6y agoA lot of the stuff you’re referring to as “application specific” is already present in Intel Macs with the T2 chip. Except obviously slower and older. People aren’t discussing it because it isn’t really “new”
- areoform 6y agoThey have indeed moved the system controller etc from the T2 onto the M1 more or less wholesale. If you look at the TEM image I have added to my post of the M1's sister chip, the A14, you'll see that the classical CPU and GPU take up only a small fraction of the die. The rest isn't memory as a naive take would suggest. It's custom silicon handling a large basket of previously CPU tasks.
- creddit 6y agoBut the cores are really good in real world, general purpose computing so I'm not sure the ASS (Application Specific Silicon) is more than half the story.
- kodisha 6y agoIt's almost 2021. Is it still ok to post paywalled articles?
- jonnycomputer 6y agoSo my 2012 MBP is on its last legs (love that thing). So now we have the M1, and I'm hearing impressive things. But my question is, as a developer who does, lets face it, pretty much the gamut, will I be handicapped in the near term? I use a combination of IntelliJ IDEs and Emacs, with MacPorts, and a large variety of open source and closed source tools. I just don't want the headache of having some part of my workflow cutoff.
- golemiprague 6y agoExactly in the same spot but I also need windows virtualisation...
- jonplackett 6y agoIn almost the same position (MacBook Pro 2013) and I plan on waiting for the 16". By the time that's out we'll see how many of these things are getting quickly ported - my expectation looking at how excited every is, is that things will get ported FAST. But there's time to wait and see before the one I actually want comes out.
- PeterisP 6y agoWell, at least Homebrew are claiming that "There won’t be any support for native ARM Homebrew installations for months to come." (https://github.com/Homebrew/brew/issues/7857 https://github.com/Homebrew/brew/issues/7857) so if you rely on a large variety of open source and closed source tools that might be a problem.
- vimy 6y agoAlmost everything works if you start terminal in rosetta mode. cmd+i on terminal.app and check the rosetta box.
- TuringNYC 6y agoSame question here, except I disagree with all the discussion on other threads about "wow, 16gb RAM is magically sufficient for most use cases." I'm sure it is now sufficient for web browsing + IDE + Slack, but what about anything beyond that? I realize 16gb RAM goes farther on M1 vs before, but some things just need RAM and there is no way around it. If i'm running a VM or multiple VMs (e.g., for android app development), or multiple docker containers -- I just need more RAM. I'm hoping that the upcoming 16" MBP upgrade offers more RAM tiers.
- mjg59 6y agoIntel will already sell you a CPU/GPU with a unified memory architecture and hardware video encode/decode. Intel's mobile parts are already SoCs (the U and Y models have the PCH on-chip, and the U's TDP range is probably the closest to the M1). These are not the reasons the M1 is faster than x86, but the article focusing on them so much means I'm more skeptical about the claims around OOP.
- SoSoRoCoCo 6y agoA few years ago, Apple's Portland, Oregon office hired dozens of top architects away from the Intel site 10 miles away (for big $$$). For those of you that don't know Oregon Hosts D1X (Intel's gigantic cutting-edge fab) and several architecture teams, predominantly veterans from the P4 product line. This probably has something to do with it.
- tigen 6y ago"Now you got a big problem, because neither Intel, AMD or Nvidia are going to license their intellectual property to Dell or HP for them to make an SoC for their machines." This isn't quite correct. AMD and Nvidia have made custom SOCs for game consoles for years now; they could create customized SOCs for PCs if this was a critical issue. But I don't believe it is. The PC workloads and use cases follow well-known patterns and market segments and you don't really need a lot of different custom accelerators, or be on a single SOC for that matter. Video-related processing has been part of GPUs for many years. For that matter, making RISC CPUs is not actually a huge obstacle for these guys. (Nvidia does.) Yes even Intel. The article also seems to entirely omit the M1's heterogenous core strategy, where 4 of the cores are high performance and the other 4 are optimized for power efficiency. A deeper analysis of this and how software manages them would be more interesting.
- Tsarbomb 6y agoNot to mention, that AMD's IO / Memory controller has a whole ARM CPU on the same die for handling their platform security.
- spideymans 6y ago>The article also seems to entirely omit the M1's heterogenous core strategy, where 4 of the cores are high performance and the other 4 are optimized for power efficiency. A deeper analysis of this and how software manages them would be more interesting. When the CPU utilization ramps up on M1 MacBooks, the user interface always remains buttery smooth. I haven't been able to make the M1 Air drop a frame yet no matter how hard I push it. Meanwhile doing anything remotely CPU intensive on an Intel MacBook will turn the user interface into a janky stuttery mess. I suspect the heterogeneous cores are the "secret" behind this. Performance tasks are delegated to the performance cores, leaving the efficiency cores free to instantly respond to any UI-bound tasks.
- rhencke 6y agohttps://en.wikipedia.org/wiki/ARM_big.LITTLE https://en.wikipedia.org/wiki/ARM_big.LITTLE might yield clues
- tommoor 6y agoI found this recent ColdFusion video on the background of ARM and RISC processors really educational, I think most will learn _something_ from it: https://www.youtube.com/watch?v=OuF9weSkS68 https://www.youtube.com/watch?v=OuF9weSkS68
- littlecranky67 6y agoI am wondering how the M1 is doing regarding the various side-channel attacks that came to live with the Spectre/Meltdown publications. Is the M1 less prone to side channel attacks by design, or is this just something not yet known?
- dylan604 6y agoI'm sure it'll be impervious to any attack vector just like the T2 chip. Oh, wait. Ooops. I'm sure all of the hackers are having a field day looking for vulns in the new chip. It'd be a hacker's fantasy to be the first one to find something on the brand new chip.
- saagarjha 6y agoThe core design is largely identical to the Apple's mobile processor line.
- dreamcompiler 6y agoAs the article points out part of the reason is that the ARM's RISC instruction set has a lot more room for optimization than the x86 CISC instruction set, which Intel has been milking since 1972. If that were the whole story, ARMs would have been faster than Intel long before now, so there's obviously much more going on than simply RISC vs. CISC. Still, I find it gratifying that my least favorite instruction set of all time may finally be going the way of the dinosaur.
- AsyncAwait 6y ago> Still, I find it gratifying that my least favorite instruction set of all time may finally be going the way of the dinosaur. Only I fear it won't be replaced by anything more open.
- KingMachiavelli 6y agoVertical integration seems to have really paid off for Apple as it's really what allowed them to pull this off. While I certainly expect cloud providers to continue adopting ARM CPUs, I'm worried that the enthusiast/DIY desktop market will be irrelevant if x86 continues to lag behind ARM. It certainty doesn't seem like buying an Ampere server is as simple as getting an x86 machine. Perhaps POWER10 or eventually RISC-V offerings will become more accessible & competitive?
- mhh__ 6y agoPower 10 does have some nice features so it would be pretty nice to see IBM seize the opportunity, not that they will.
- faitswulff 6y agoRegarding vertical integration, I wonder if their owning the OS and the hardware stacks lead to special insights on what would lead to better performance.
- _ph_ 6y agoAnd they are completely unconstrained in where to put the compute. They can decide to add new special hardware to the SOC and just support it in the OS.
- raverbashing 6y agoIt's an interesting take, and I agree with the issue being the x86 difficulties. There was a link today about "how many registers an x86 processor has" and it really reminded me of how many issues and legacy the processors have to deal with I think the solution would be to move the x86 cruft to an SW emulation layer, and focus on base performance. Something like this (though I'm skeptical of taking things like rings and memory protection out of hw http://www.emulators.com/docs/nx03_10fixes.htm http://www.emulators.com/docs/nx03_10fixes.htm ) Your latest Intel chip boots like an 8086 from the 70s and it has to do several steps before it goes to protected mode. It has to deal with x87, MMX, SSE, SSE2, AVX etc (ARM has NEON and that's it.). Every register has several ways of being accessed: AH/AL, AX, EAX, RAX. Wanna access a partial part of a register on ARM? AND/Shift.
- mhh__ 6y agoX86's legacy really only affects the decoding logic, whereas the actual CPU itself could be almost any superscalar execution stage (simplified). For example, amd64 has about 20 general purpose registers, but the silicon that actually executes it could have something like an order of magnitude more to play with (i.e. for register renaming)
- raverbashing 6y agoFrom the article > If we have more decoders we can chop up more instructions in parallel and thus fill up the ROB faster. > And this is where we see the huge differences. The biggest baddest Intel and AMD microprocessor cores have 4 decoders, which means they can decode 4 instructions in parallel spitting out micro-ops. > But Apple has a crazy 8 decoders. Not only that but the ROB is something like 3x larger. You can basically hold 3x as many instructions. No other mainstream chip maker has that many decoders in their CPUs. > You see, for x86 an instruction can be anywhere from 1–15 bytes long. On a RISC chip instructions are fixed size. Why is that relevant in this case? > Because splitting up a stream of bytes into instructions to feed into 8 different decoders in parallel becomes trivial if every instruction has the same length.
- tehjoker 6y agoSo in the (excellent) article, they have two advantages: System on a Chip and enhanced out of order execution. Wasn't out of order execution implicated in Spectre and Meltdown? How are they mitigating this issue? I imagine for a new chip they could design something in.
- annilt 6y agoOut of order execution makes your code run faster like 20x-50x. You can’t produce a CPU without it and compete in the market. There are many variations of spectre and meltdown bugs, some of them might be fixed in the CPU and some in the OS. So, there is no simple answer to your question I believe.
- tehjoker 6y agoI would just wonder if increasing the quantity of OoO makes mitigation more difficult in some way.
- annilt 6y agoAfaik all spectre/meltdown family attacks are possible even with a single OoO execution. But increasing the quantity(adding more complexity) might cause new batch of security issues ofcourse.
- gameswithgo 6y agoThere are some technical things I feel are somewhat misrepresented: 1. Why don't AMD/Intel use a unified GPU/CPU memory setup like Apple? Because the big discrete gpus would be too big and hot to be part of the same chip as a cpu, and need faster memory than DDR4. 2. Zen3 is clocked at 5ghz: the best of them can turbo to 4.9 for a little bit, base clocks are ~3.4 to 3.8 depending on core count / model
- socialdemocrat 6y agoThere has been talk of using eGPUs with the M1 chips. Obviously there would be downside to having to move stuff over a slow Thunderbolt 3 connection but given that the GPU can be much bigger, how do you think that would play out? Would that offer higher performance? If so on what kind of workloads?
- baybal2 6y ago> Why don't AMD/Intel use a unified GPU/CPU memory setup like Apple? Well, they do, for like 10+ years now
- avmich 6y agoRequires an account. Is there a less restricted URL for the story?
- npiit 6y agoApple M1 is so fast because you paid a lot for it and want to feel good about that I guess.
- spamizbad 6y agoGotta say I'm not a fan of this article. A few points I really disagree with: 1) It puts way too much emphasis on the ISA being a driver for performance. People have been making this claim against x86 forever, going back to the 90s when RISC chips started putting up some very impressive performance numbers. Lots of talk about how the x86 ISA was out of runway. This period existed fo a grand total of about 4 years (94 thru 97) until the Pentium II hit the market, which allowed PCs to start cutting into the workstation market. AMD creating the x86-64 extension handled the addressing limitation well too, letting it flourish in the server space as well. 2) The author seems to think Intel or AMD cannot make SoCs because of their business model. This really isn't the case, and both companies have slowly been moving more "stuff" on package. AMD is already there with the xbox an playstation chips they manufacture. AMD's chiplet approach would be particularly adroit at exploiting this. I get the feeling both AMD and Intel would LOVE it if PC vendors started demanding SoCs. And while the M1 has lots of little speciality processors onboard, both AMD and Intel have more robust processor I/O. That's by design: The M1 isn't designed for the person who needs a gazillion PCI-E lanes for storage and networking (the M1 is likely has half the PCI-E lanes as consumer Zen2/3 cpus and 1/4th to 1/8th compared to Threadripper and EPYC) 3) Glosses over the fact that one of the greatest challenges in computer architecture is coping with the so-called "memory wall": there's a growing latency chasm between cache and memory. Apple cleverly mitigates this by using very fast, low latency memory (LPDDR4x 4266 MT/s vs DDR4 at 3200 MT/s in x86 CPUs). But beyond how many MT/s you're operating with, I would love to see some latency figures. They likely blow your typical consumer DIMMs out of the water. Both AMD and Intel wok around this limitation with larger caches and smarter prefetching, but that only gets you so far. edit: And I would wager much of its impressive performance figures comes from Apple's approach to addressing the memory wall. Memory latency benchmarks seem to strongly favor the M1 over both AMD and Intel CPUs.
- pclmulqdq 6y agoThe Intel ISA has some very powerful instructions that allow it to keep performance up, but unfortunately decoding n x86 instructions involves doing a number of things that are O(n) in latency and O(n^2) in chip area/power - both instruction boundary detection and micro-op scheduling (since instructions can emit more than one uop) are included here. This isn't too bad when n is 4, but it has stressed both AMD and Intel's capabilities to make it to 8, and I don't think anyone would ever seriously consider building a 16-wide x86 machine. Once memory and I/O buses get fast enough to feed a 16-wide general-purpose computer, x86 as an architecture is in trouble. They have quietly gotten fast enough to feed an 8-wide machine. LPDDR4 very quietly took the speed crown from DDR4 due to the fact that the signal integrity problems are less demanding (soldered vs DIMM being the standard interface), and it looks like the DDR interface may be near the end of its useful life. Transceiver-based memory modules using standards like CXL and CCIX may be the long-term fix to the problems of DDR4. In the short-term, those are going to hurt, but long-term they should be a lot better.
- pkulak 6y agoAll these specialized co-processors make me a bit sad. I've already got a graphics card that can decode some video formats, but not new ones, and that will never change until it becomes e-waste. Now we get the same thing for image formats, ML, etc? And you're even more locked in to these co-processors since they use space that could have been used to have a dozen general purpose cores. So good luck ever watching a video that doesn't use a codec your hardware supports.
- amelius 6y agoI'd be ok with coprocessors if there was an easy way to swap them in and out.
- greyhair 6y agoA lot of modern hardware coprocessors are hybrid blocks that can be configured through firmware. You can dedicate a very small DSP with the block to feed and manage it. I haven't been involved in a new chip design in a few years, but a lot of specialized cores were vector processors (very narrowly defined vector processors). I don't know if that has changed. I find it surprising that you have a graphics card that won't decode new video formats, unless the vendor has completely abandoned support for it. I have never encountered a modern graphics card that wasn't completely configured and run with firmware.
- pkulak 6y agoMaybe I just don't pay attention, but I've never heard of new firmware going out to multi-year old graphics cards and adding new features. Sure it may be possible, but what company is going to go through the trouble of that?
- randerson 6y agoA lot fewer molecules of e-waste with the tiny SoC, at least.
- FullyFunctional 6y agoI'm am very appreciative to Apple for finally closing the endless "The ISA doesn't matter" nonsense. The ISA does matter and it's part of what enabled Apple to go so wide. However, there the article is slightly misleading. The ROB isn't where instructions are issued from, that would be the schedulers which usually holds a much smaller set of instruction (16 per scheduler is common). The ROB holds everything that was decoded and not yet retired, thus including instruction that haven't yet been issued to schedulers and more importantly, instruction that have been executed for not retired (eg. might be waiting on older instruction to retire first).
- saagarjha 6y agoHistorically, I have yet to see a single case where the ISA has mattered. Every ISA will of course take advantage of its unique features, but in general fast chips come from companies with money and talent, not a particular ISA.
- ridiculous_fish 6y agoI think Itanium mattered. Its EPIC instruction set tried to push the scheduling complexity from hardware into the compiler, which proved too difficult. That's part of why it failed.
- FullyFunctional 6y agoGreat example. Seeing as I'm working on my Merced box I felt like commenting on this. Intel/HP did many things wrong when they designed EPIC. The absence of dynamic scheduling was supposed to have made it simpler and thus have a faster cycle time. Alas it was so bloated when it finally arrived and horrendously complicated that it clock very slowly (mine @ 733 MHz while contemporaries ran at 1+ GHz). The EPIC designers probably also didn't anticipate the advances in OoO machines that got really good. Trying to statically schedule for unknown load-misses isn't just difficult, it's impossible without code explosion. EPIC got some things right, but design by committee and betting again dynamic scheduling doomed it.
- jhallenworld 6y agoI (as a tech lead in IBM) had a sales visit from P.A. Semi years ago- we needed a CPU for a co-processor board. We didn't use their chip, and I was amazed that Apple bought them soon after. But then consider who was the founder: https://en.wikipedia.org/wiki/Daniel_W._Dobberpuhl https://en.wikipedia.org/wiki/Daniel_W._Dobberpuhl
- mbroncano 6y agoRecently passed, RIP
- faitswulff 6y agoEveryone talks about its top scoring benchmarks, which I presume are the Firestorm cores, but I have to wonder what engineering marvels went into the Icestorm cores?
- greyhair 6y agoInteresting article here, but a lot of the stuff laid at Apple's feet here did not begin at Apple. Yes, they implemented it in a high power design, and yes, they did a great job, and it is really performing well, but all of this has been common in cell phone chips available from various vendors for over a decade. Multiple cores, multiple DSPs, ISPs, GPUs, secure enclaves, encryption engines, high speed serial controllers, ADC/DAC, plus all the stuff to support the cellular modem such as viterbi encoders/decoders. All these little specialized blocks all embedded on the chip, and the DDR soldered directly to the top of it. This has been a common technique for over a decade. Why isn't your phone as fast as the M1? How long do you think the M1 would run on your cell phone battery? Everything is an engineering trade off. So Apple basically took the last decade of smart phone architecture, and blew it up with more transistors, to accomplish more processing throughput. They didn't invent the technique of hybrid multi-core silicon by any stretch of the imagination. You can go back to the mid 1990s and find single chip 56K dialup modems with a general purpose CPU, a DSP, onboard RAM, onboard NOR FLASH, and a half dozen dedicated modem hardware blocks, all on a single die.
- saagarjha 6y agoMy phone is has comparable single-threaded performance with an M1. But it happens to have an A14 chip inside it ;)
- wffurr 6y agoApple is about three years ahead of any other mobile chip maker. Sure, it's the same type of SoC and general architecture, but somehow Apple's CPU and GPU designs are miles ahead of anyone else.
- fomine3 6y agoCPU is exceptionally great but I don't think Apple is also leading GPU. I doubt M1's GPU efficiency is mostly came from 5nm process.
- superjan 6y agoI wonder, has anyone written about to what extent XCode has been optimized for the M1? With the wide decoder loop unrolling gets a lot more attractive....
- Thaxll 6y agoAlso isn't Apple has it "easy" designing a chip from scratch with 0 backward compatibility + they manage the HW + SW. Intel & AMD have to support thousands of different config: - I can plug my old memory it works - I can plug my old graphic card it work ( PCI-e ) Apple has 0 constrains about legacy hardware, software ( beside that emulation layer ), so yes it's a great achievments, but it's very different from designing a chip for PC.
- saagarjha 6y agoYou put "that emulation layer" in parentheses but it's no trivial feat writing an x86/x86_64 emulator with high enough fidelity to run almost all Mac apps at almost native speeds.
- ridiculous_fish 6y agoFurthermore the M1 has some hardware support for this, via a runtime-toggle to force x86-style total store ordering.
- ebg13 6y agoEvery discussion thread about M1 has a dozen people saying "Give me a 64GB M2 with more cores and more ports and I'll buy one." But I just want a 15 inch M1 Air. For most people 16GB and 4+4 is more than enough, and it's the larger screen that differentiates the models.
- amelius 6y agoDid Apple patent anything in their chip?
- letwhile 6y agostop posting paywall shit. wtf
- majewsky 6y agoQuestion for the chip design crowd here: Would it be feasible for Intel/AMD to design a fast ISA from the ground up and add it as a runtime option to their x86_64 chips? Like, on context switch to userland, the kernel puts the chip into whatever ISA is in the respective process's binary. And the syscall instruction and interrupts put the chip back into the kernel ISA. So you would have backwards compatiblity, but new stuff could use the faster ISA. I guess my main question is if there would be enough die space to support two separate instruction decoders.
- greyhair 6y agoThe short answer is no. Basically, you are asking them to really have two sets of cores on a single die and switch back and forth. I think the more realistic point of view is that x86 has likely run its course, and now it is time to move on. The long answer is look up Transmeta and do some reading. Basically they designed a RISC CPU core with an external microcode engine, that was able to run x86 instructions. It was a valiant effort, but it didn't work as well as hoped. Here is a fun history read that mentions Transmeta as well as P.A.Semi. P.A.Semi is the core team that designed the A1 (and following Apple cores) after being bought by Apple in 2008. Prior to that, the team had designed the DEC Alpha (awesome processor) and StrongARM cores. Later, they developed PowerPC cores. A team with really deep CPU talent, and in particular, prior ARM ISA experience, when they were acquired in 2008. Sorry, I forgot the link on the first post.... https://www.linleygroup.com/newsletters/newsletter_detail.php?num=4139 https://www.linleygroup.com/newsletters/newsletter_detail.ph...
- monocasa 6y agoYou say no, but the PowerPC 615 is an example of a core which did that. You just need two instruction decoders (and get to keep one of them off at a time, which is awesome for dark silicon reasons).
- ridiculous_fish 6y agoThis is what Intel attempted with Itanium. The hardware implementation was too slow so they pulled it. More recently is Nvidia's Denver project, which has a private ISA and dynamically translates ARM instructions. It's an open secret they had it working for x86 too, but it was scuttled due to patent threats.
- vladletter 6y agoHello! Thanks for the sharing, would have been nice not doing that on Medium, it's not free anymore. But thanks again!
- Sparkyte 6y agoI just had to jump on here to say how wrong the article is on numerous things. - Ryzen is an APU - No it's an SoC the northbridge and memory controllers are on the CPU. All Ryzen are SoC. - Ryzen also contains the memory controller on circuit. - CISC vs RISC - While CPUs are fundamentally this nature for x86(CISC) and ARM(RISC) they both carry similar on level instruction sets today a mix of complex and reduced. Why is Apple's chips better at the moment? Because they actually been throwing money into the RND of the processor. cough intel cough You actually see the same perf gains on AMD since it can now flex it's muscles. AMD laptops are getting 10+ hour battery life. If we give AMD a few more years the perf will probably escape the M1 since the chiplet design scales better.
- ehejsbbejsk 6y agoI think what will make Apple Silicon a success is that they are not going to purposely slow down progress for the sake of sales and marketing. Apple is still an engineering-driven organization, despite their marketing genius. They’re not going to intro filler products here and there to squeeze the market.
- declnz 6y agoInteresting article, and call my cynical but wasn't anyone else immediately reminded of the excellent HN post earlier this month [1], and the Apple big-picture play proposed there? "Those shiny new Apple Silicon macs that Apple just announced, three times faster and 50% more battery life? They won’t run any OS before Big Sur." [1] https://sneak.berlin/20201112/your-computer-isnt-yours/ https://sneak.berlin/20201112/your-computer-isnt-yours/
- cromwellian 6y agoCouldn't Intel and AMD implement a "Rosetta2" like strategy? That is, couldn't they ship CPUs that fundamentally are not decoding x86 ops, but some different ISA, and then layer a translation layer on top of it? The Transmeta Crusoe used to do this, and I think the NVidia Denver cores did too? I think fundamentally though this analysis highly depends on single-threaded performance being the bottleneck for most apps. A lot of sophisticated workloads are GPU or TPU driven, and so hand-waving away multi-thread performance, and treating single-thread performance as the end-all for client side performance I think is overemphasizing its importance. Also, the "they don't control the stack" argument is wrong. Effectively, Intel/AMD + Microsoft acted as a duopoly, and if you toss in NVidia, the structure of DirectX and Windows is largely a cooperative effort between these OEMs. If Intel/AMD needed some fundamentally new support for some mechanism to boost Windows performance by 20-30%, Microsoft would work with them to ship it.
- klelatti 6y agoThe PC world has already switched architectures 32 bit to 64 bit already so its doable. The big issue I think is if you are Intel / AMD why would you do this? Even if there are performance gains do you really want to undermine one of the things (backwards compatibility) that distinguishes you from the competition? Plus what would the new ISA be? Plus Intel still has the memory of Itanium.
- djtriptych 6y agoAs someone who's generally been tech-aware for decades, this seems like a revolution. I've never seen reviews like this. I keep buying AAPL. I think they're going to eat Intel.
- fancyfredbot 6y agoA lot of people are asking why Intel or AMD haven't produced a CPU like this, but that's not so interesting to ask because maybe that's something to do with the x86 ISA. What about Qualcomm, ARM, and Samsung though? What's their excuse?
- hocuspocus 6y agoMaybe it simply doesn't economically make sense for Qualcomm and even less so for Samsung. Their SoCs equip a lot more entry-level or mid-range low-margin phones, compared to Apple. There might be the need to make more powerful, desktop-class SoCs in the future if Google and Microsoft push for that. But I imagine the real competition will come mostly from the server market for now. Unless Nvidia starts making beefier SoCs, maybe the upcoming Orin.
- sys_64738 6y agoWhat do we know about the memory model? I see refs to not copying memory which suggests there isn’t even any L1 cache on die. Is this true? Anybody got a detailed arch diagram of the M1’s memory hierarchy?
- bahmboo 6y agoAs a person who has written tons of machine and assembly code and dealt with decades of working directly with the cpu: this is a well written and accurate article.
- nazgulnarsil 6y agoGood packaging and TSMC's better than expected results are certainly a big part of the picture. TSMC: '5nm yielding better than 7nm.' Apple can put the higher leakage chips in mac minis where they can afford to pump more power through.
- breatheoften 6y agoI've been wondering what kind of hardware optimizations might be possible based on tagged pointers? If you know a memory location is uniquely referenced for example when you load or store ...
- aclindsa 6y ago> So e.g. smaller ARM CPUs don’t use micro-ops at all. But that also means they cannot do things such as OoO. Perhaps I'm picking nits, but the second sentence is not true. The dependency/resource-tracking and scheduling required for OoO execution do not depend upon using micro-ops.
- da39a3ee 6y agoIf, in an alternate universe, the people who have designed the amazing hardware we have today suddenly switched to work on designing web backends of medium-sized tech companies, would they do a better job than the random mess of databases, services, microservices, HTTP APIs, GraphQL APIs, client-side logic, server-side logic, etc that we have today?
- dirtypersian 6y ago"RISC CPUs have a choice. So e.g. smaller ARM CPUs don’t use micro-ops at all. But that also means they cannot do things such as OoO." I don't agree with this. What do uops have anything to do with ooo execution. I can easily make a CPU with no uops doing ooo execution. Unless I'm misunderstanding and the article is just saying smaller cores don't do ooo since they are trying to stay within a certain area/power footprint.
- jet_32951 6y agoThanks, @socialdemocrat, that is a good intro for someone (like me) who doesn't understand hardware architecture.
- socialdemocrat 6y agoGreat! I thought there was many people who wanted some in depth discussion but which did not necessarily have a lot of prior knowledge about the topic. E.g. Anandtech gives a lot of great detailed info, but hard to read if you are not a regular reader of their website.
- phendrenad2 6y agoI still don't get why they didn't use RISC-V. Sure, they have an ARM license, but running existing ARM software on the M1 doesn't seem very useful. Why not use the superior ISA?
- fomine3 6y agoWhy use different arch to iPhone/iPad? M1 borrows most design from A chip and they spent time to optimize software for Arm.
- CivBase 6y ago> In real world test after test, the M1 Macs are not merely inching past top of the line Intel Macs, they are destroying them. In disbelief people have started asking how on earth this is possible? I'm getting sick of this. The M1 is an impressive chip for sure, but it's ridiculous to compare them to the Intel chips in last year's MacBooks. Those chips were old, the cooling solution was terrible, and Intel had already fallen way behind AMD for the kinds of tasks you might actually use a MacBook for. The cynic in me thinks Apple intentionally handicapped the 2019 models to make the M1 look as good as possible... and it clearly worked. Can we please stop comparing apples to oranges (pun intended)? Like I said, the M1 is impressive - especially in terms of power efficiency - but we should be comparing it to the likes of an Intel Core i7-1185G7 or the imminent AMD Ryzen 7 5800U.
- caribbeanblue 6y agoWhat are you talking about? The last gen Macbook Air and Pro had Ice Lake chips with Iris Plus graphics, why would that be not a fair comparison? Sure, the Air did have a terrible cooling system, but so does the new Air. The 2020 4-port 13” Macbook Pro that still continues to be sold as they’re the only 13” Macbooks that can be configured with 4TB SSD and 32GB RAM as of now, has a 4-core Ice Lake that Apple literally push to its limits to squeeze every ounce of performance they can, if you watched a review or two covering that machine. Linus Tech Tips complained that it was running too hot — not thermal throttling, just going really fast. And the M1’s GPU is like 2-2.5x faster than even those machines’ iGPU.
- supernova87a 6y agoI'm super curious -- since Apple is not marketing on Ghz and playing the Intel game, how do they deal with variable chip manufacturing yield? Is there a narrow band or minimum chip speed that they'll accept and toss anything performing below? Does the SoC become so physically larger that yields also go down by quite a bit, and any defects on 5nm become much more troublesome?
- sliken 6y agoAnyone wanting linux on the M1 there's now a patreon at https://www.patreon.com/marcan/ https://www.patreon.com/marcan/
- raiyu 6y agoThe whole m1 vs intel and AMD saga reminds me of innovators dilemma and the lesser referenced investors solution by Clayton Christensen. In the solution book it basically details that everything goes through an ebb and flow of aggregation and disaggregation. This was often pointed out with Craigslist as the original aggregator and how many startups have been founded now to disaggregate it. Interesting to read this article from that perspective. Intel and AMD disaggregated and found success for decades but now aggregating with SoC looks to yield massively better results. Interesting to see certain business patterns continue to reappear. Also shows that in tech no one has dominance if they don’t adapt.
- pmontra 6y ago> Sure Intel and AMD may simply begin to sell whole finished SoCs. But what are these to contain? PC makers may have different ideas of what they should contain. There used to be many competing CPUs with different instruction sets. I personally used z80*, 6502, 680xx, 80xx, Alpha, one from HP and who knows how many others. Add PowerPC and was Itanium a not x86 CPU? Then we almost standardized on one for a long time, plus ARM lately. No reason for we won't standardize on one SoC. It could be everybody buying only Apple computers (unlikely) or some company winning the forthcoming SoC wars. Or business as usual and stay on the current general purpose architecture forever, which is also unlikely given the optimization advantages of a SoC like the M1.
- fractallyte 6y agoSo they have 'co-processors', like the Amiga, but on a chip! Recall, this is what made the Amiga such a groundbreaking computer back in the 80s and early 90s: separate co-processors that handled graphics, sound, DMA, IO,... It worked (for a while) because the Amiga was an integrated system of hardware-and-OS - exactly like Apple. Unlike the MS-DOS and Windows PCs of the time, there was no need to support third-party hardware. Together with a really nice OS, the platform encouraged creativity and gave rise to a generation of coders, artists, and musicians. So everyone: now you know what it felt like when the Amiga first appeared on the home computing scene!
- Michael_Sieb 6y agoCant wait to see this chip in the 16-inch.
- helsinkiandrew 6y ago> Sure Intel and AMD may simply begin to sell whole finished SoCs. But what are these to contain? PC makers may have different ideas of what they should contain. You potentially get a conflict between Intel, AMD, Microsoft and PC makers about what sort of specialized chips should be included. It will be interesting to see what happens to the Wintel business in the years to come - is this the beginning of the end? If Apple can build a strong price/performance advantage in a way that can't be replicated by PC makers and, for example, start bringing out cheaper 'SE' versions of their laptops.
- rocqua 6y agoWith out of order execution being apparently a big deal here, what are the odds of side-channel attacks based on this OoOE being found for this architecture?
- warpspin 6y agoThe one thing that still puzzles me is, how that unified memory thing works and actually handles contention between GPU and CPU without slowing either down. There's not much information out there how it actually works. Anybody has any details?
- ralphc 6y agoCouple of years back I bought a big gaming laptop to do ML and deep learning on, TensorFlow, Keras, all that. i7 and NVidia 1080, 8G of GPU ram. I know TensorFlow has been ported to Big Sur/M1, anyone know how well it performs with sharing memory between CPU and GPU?
- zaro 6y agoI don't understand why the bug fuss about M1. After all M1 is 5nm CPU. AMD Renoir is better than Intel for the same reason, it's 7nm while Intel can't get below 10nm yet. So while M1 is probably a great CPU I expect its advantages will mostly vanish once AMD and Intel move to 5nm also.
- lenkite 6y agoSo basically Intel shouldn't have abandoned Itanium.
- zuhrik 6y agoAfter analyzing the benchmarks I have a suspition that the apple compiler does some automatic parallelization and issues some instructions on the GPU, since the GPU shares the memory coherency with the CPU. That's why roseta2 performance is slower, as optimizing loops on the binary is harder. If they are not doing that, they should, as it will be something like an AVX512 for the poor energy budget. Just lunching a debate, as the wide decode with long pipeline smels like a Pentium4 crap or a miracle.
- Karuhanga 6y agoI suspect Intel will in the future have separate processors which can less painfully take advantage of more decoders, perhaps with a restricted instruction set?