_chris_

9 ms·

61.
by _chris_ 7y ago
There were a ton of talk submissions, and the schedule is incredibly tight because of it. =(
62.
by _chris_ 7y ago
It's still a work-in-progress, but there should be some interesting news at the RISC-V Zurich conference next week [1]. For example, Imperas has announced an ISA simulator for the current 0.71 version of the specification [2]. [1] ( ht
63.
by _chris_ 7y ago
For starters, you need a mechanism to notify other cores that their instructions have changed. That may mean requiring coherent icaches, or maybe some more explicit but simpler mechanism.
64.
by _chris_ 8y ago
> It requires Gtkwave to view waveforms with (opinion, but I hate the UI) It dumps a value-change file (vcd) which can be viewed by anything, no? Sure it's not very compressed (and the compile-time for vcd-generation is unfortunat
65.
by _chris_ 8y ago
> When you have a look at the SweRV architecture and implementation, it is not incredibly complex, especially compared to, an out-of-order triple-issue A-15 core. And yet it achieves similar or higher CoreMark/MHz scores. FYI, Cor
66.
by _chris_ 8y ago
Too far away and requires huge thread counts to make up for its overheads. A good vector unit should work well even for very short vectors (e.g., any size of memcpy).
67.
by _chris_ 8y ago
The core speaks AXI and AHB-Lite, so for an experienced FPGA/core guy, it probably wouldn't be too much work to integrate into their own FPGA flow. And since it doesn't have any floating-point, it will probably be able to fi
68.
by _chris_ 8y ago
> Do HN readers have an unusual like for ‘small’ phones or is it just an unserved market? My wife wants a phone that can fit into her jean pockets. Requiring handbags just to carry a phone around is absurd, and untenable for many peopl
69.
by _chris_ 8y ago
10 years ago; I'd really like to hear a post-mortem of this decision. For context, MIT's previous EECS curriculum began with 4 required courses for all EE and CS majors. This meant that EEs had to suffer through Scheme, and CS&#x2
70.
by _chris_ 8y ago
In comparing RISC-V vs MIPS, I think people are forgetting that one is a Foundation of member companies driving development, and the other is one company releasing their IP. There's obvious pluses and minuses to both approaches, but if
71.
by _chris_ 8y ago
And in video form, if that's your thing: https://www.youtube.com/watch?v=_mZORF2vHAA&feature=youtu.be... .
72.
by _chris_ 8y ago
No, the IO plumbing and infrastructure are different. FPGAs are a total pain because each platform is different. :'(
73.
by _chris_ 8y ago
I don't remember numbers (and resources aren't always apples-to-apples), but it's bigger than a Zedboard and 60% of a zc706 I believe. It's a ton of wires is the big issue I suspect.
74.
by _chris_ 8y ago
My parents thought it was quite odd that I named it the Berkeley Out of Order Machine. "Why would you advertise to the world that it doesn't work?"
75.
by _chris_ 8y ago
Unless you cut out floating point and superscalar, it requires a fairly large FPGA, on the order of >$1000. So you'd have to put it to serious use to break even with using AWS. The other advantage of AWS is scale-out once you want t
76.
by _chris_ 8y ago
It's been over 10 years now. Is there a good post-mortem on the outcome of the switch away from 6.001 and Scheme?
77.
by _chris_ 8y ago
> But I'm not quite sure what's holding up general purpose CPUs (even just something crappy/good-enough).. The way I understand it CPUs aren't just beefy microcontrollers and they require some extra onchip hardware,
78.
by _chris_ 8y ago
I'm pretty sure adding a more restrictive license clause is a fork of the code base and any new code commits would use the newer, more restrictive license.
79.
by _chris_ 8y ago
Sandsifter is dealing with the problem of "how do I find valid instructions in any 1-15 byte sequence, which yields 2^120 combinations?" In RISC-V there are currently only 2 byte and 4 byte instructions, which you can brute force
80.
by _chris_ 8y ago
RISC-V is pretty nice in that the ISA gets out of your way, and you can focus on the techniques to build a high-performance processor without wasting effort on legacy and other weird corner case behaviors. A++, would recommend. However, if
81.
by _chris_ 8y ago
I gave a talk on this topic at a recent RISC-V conference (slides here: [1]). I think this can entirely be hidden below the ISA abstraction, but it will be a lot of development work to do this and unfortunately getting new hardware into the
82.
by _chris_ 8y ago
If your processor uses register renaming, the frequency of your core limits how many physical registers you can have in the register file. Therefore, you are incentivized to split integer and floating point register files so you can size up
83.
by _chris_ 8y ago
Nope, just a small batch test-chip run. And even out of a few dozen chips, I think we only did packaging for ~5 chips. It boots Linux, but at 6 mm^2, it's not really big enough to contain an on-chip memory controller, so going out to D
84.
Healthy Discussion of Architectural Choices: Response to ARM’s Critique of RISCV(eetimes.com)
2 points by _chris_ 8y ago|0 comments
85.
by _chris_ 8y ago
Adapteva did not use RISC-V. Andreas Olofsson said that, if there was another version, he would probably use RISC-V. [ http://www.adapteva.com/andreas-blog/why-i-will-be-using-the... ]
86.
by _chris_ 8y ago
https://01.org/security/advisories/intel-oss-10002 (CVE-2018-3693).
87.
by _chris_ 8y ago
And then they started raising the licensing fees. Man what bad timing.
88.
by _chris_ 8y ago
Off the top of my head, Western Digital and NVIDIA have both announced using RISC-V in their upcoming products.
89.
by _chris_ 8y ago
I think you underestimate just how many hardware startups there are and how many of them are NOT going to license an ARM core for their service core.
90.
by _chris_ 8y ago
Apologies, I may be speaking out of my $(# on that. I'm aware Clifford has used it to demonstrate formal method techniques, but I don't know the full extend to it. Caveat Emptor to anyone who decided to rush out and add it to thei

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