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> When you have a look at the SweRV architecture and implementation, it is not incredibly complex, especially compared to, an out-of-order triple-issue A-15 cor

> When you have a look at the SweRV architecture and implementation, it is not incredibly complex, especially compared to, an out-of-order triple-issue A-15 core. And yet it achieves similar or higher CoreMark/MHz scores. FYI, Coremark fits entirely within an L1 cache, so performance is significantly effected by load-to-use and load-to-load delay. The "skewed" pipeline design of SweRV helps it really shine here! The OOO cores typically have worse load-to-use and the OOO advantage typically shows up once you start missing in the L1 cache. The remaining significant factor to Coremark performance is a good branch predictor, and to that end, I'm very impressed that their gshare can completely learn Coremark.

tyingq 8y ago
Also, SwerRV doesn't have an MMU, so a comparison to an A15 is a bit odd. They wouldn't have the same use cases at all.
- tverbeure 8y ago
  Author here. My reason to choose the A15 was because it was shown on the WD performance slide with a performance that's close to the SweRV. The target use cases of the SweRV are obviously very different from the A15 (lack of MMU, lack of Dcache, lack of floating point will indeed do that). But I didn't expect that adding these features would have a significant impact on peak performance of a benchmark that can fit completely in a cache? My comment about complexity is entirely about the core execution pipeline: OoO vs in-order, number of pipes, number of ALUs. Even there, the A15 is significantly more complex than the SweRV, yet it performs more or less the same in best case circumstances. I expected at least some benefits? Since that is not the case, I assume that this complexity helps for non-ideal use cases (which the SweRV will probably never experience.) Edit: as _chris_ points out: OoO helps when you start missing the L1 hits.
  - tyingq 8y ago
    Makes sense. It pops in my head because any RISCV story here usually gets flooded with people hoping for an affordable RISCV chip that will run Linux. I figured the comparison might spawn some false hope :)

tyingq 8y ago

Also, SwerRV doesn't have an MMU, so a comparison to an A15 is a bit odd. They wouldn't have the same use cases at all.

tverbeure 8y ago
Author here. My reason to choose the A15 was because it was shown on the WD performance slide with a performance that's close to the SweRV. The target use cases of the SweRV are obviously very different from the A15 (lack of MMU, lack of Dcache, lack of floating point will indeed do that). But I didn't expect that adding these features would have a significant impact on peak performance of a benchmark that can fit completely in a cache? My comment about complexity is entirely about the core execution pipeline: OoO vs in-order, number of pipes, number of ALUs. Even there, the A15 is significantly more complex than the SweRV, yet it performs more or less the same in best case circumstances. I expected at least some benefits? Since that is not the case, I assume that this complexity helps for non-ideal use cases (which the SweRV will probably never experience.) Edit: as _chris_ points out: OoO helps when you start missing the L1 hits.
- tyingq 8y ago
  Makes sense. It pops in my head because any RISCV story here usually gets flooded with people hoping for an affordable RISCV chip that will run Linux. I figured the comparison might spawn some false hope :)