3 ms·
For starters, you need a mechanism to notify other cores that their instructions have changed. That may mean requiring coherent icaches, or maybe some more expl
by _chris_ 7y ago
For starters, you need a mechanism to notify other cores that their instructions have changed. That may mean requiring coherent icaches, or maybe some more explicit but simpler mechanism.
- monocasa 7y agoIf you don't go with coherent I-D caches, is that really cheaper than IPIs?