I gave a talk on this topic at a recent RISC-V conference (slides here: [1]). I think this can entirely be hidden below the ISA abstraction, but it will be a l

I gave a talk on this topic at a recent RISC-V conference (slides here: [1]). I think this can entirely be hidden below the ISA abstraction, but it will be a lot of development work to do this and unfortunately getting new hardware into the field is a slow process. One part of this is buffering and killing speculative updates (or flushing on "time domain" switches). The other, and harder part, is to manage/avoid bandwidth contentions caused by speculation. I think the better, long-term solutions will involve address IDs/capabilities to better denote security boundaries to the hardware. But that requires a lot of buy-in across many layers of the compute stack(OS/platform change for starters). [1] https://content.riscv.org/wp-content/uploads/2018/05/13.00-13.15-Celio-Barcelona-Workshop-8-Talk.pdf https://content.riscv.org/wp-content/uploads/2018/05/13.00-1...