_chris_

14 ms·

91.
by _chris_ 8y ago
Let's say I'm making an SoC and I need an always-on service processor. It's a waste of effort for me to make it myself, so I'll either license one or grab one off the internet, if I could trust it. In the past, people ju
92.
by _chris_ 8y ago
Thanks for the link! I should've been more precise: the question in my mind is how many kbits/second of arbitrary target memory can be leaked. That's what made Meltdown/Spectre so scary was that the entire kernel memory
93.
by _chris_ 8y ago
> So... they "strongly suspect" (but don't know and haven't shown) there may be a Spectre-class bug enabled by current HT implementations Spectre is about a) leaving side-effects of misspeculation in shared resource
94.
by _chris_ 8y ago
VLIW compilers construct a "bundle" of instructions which are to be executed simultaneously, and thus must be completely independent of each other. The VLIW compiler must further space "bundles" apart such that any use-b
95.
by _chris_ 8y ago
Yes, you can buffer up and kill any misspeculated updates. You have to do this for ALL shared structures, not just data caches. Annoying, but not impossible. The scarier part is managing bandwidth contention to shared structures.
96.
by _chris_ 9y ago
I assume you meant to reference this, but just to make it clear, those old gaming console cartridges sometimes DID have special chips in them. Much to the horror of emulator writers a decade later, hehe. Wiki: https://en.wikiped
97.
by _chris_ 9y ago
"Purpose-built" means you can change the ISA to suit your whims, which for ARM requires you to A) pay for an architecture license and B) pay for the privilege of changing the architecture.
98.
by _chris_ 9y ago
Cost of the wafer is fixed. The smaller the chip, the more chips per wafer, and thus, the cheaper each chip is. Then add defects to that, which means you have to throw away more silicon per defect the bigger the chip.
99.
by _chris_ 9y ago
Load-reserve, store-conditional, and atomic memory operations (e.g., AMO-ADD).
100.
by _chris_ 9y ago
I learned from MIT's 6.004. They provide infrastructure for you to build a simple core from gates for a RISC ISA in their own test environment. Their materials should be online (or available via OCW).(E.g., https://www.youtu
101.
by _chris_ 9y ago
You tag things and prevent bypassing uncommitted data from one thread to another. For example, it's a mistake (that's been made by other ISAs!) to allow two hardware threads to bypass store data out of the uncommitted StoreQueue f
102.
by _chris_ 9y ago
It's been taped out as a research chip, but no production runs. Naturally, like any OOO-issue processor, it supports speculative issuance of load operations to the memory system (or it wouldn't be worth the effort of OOO-issue).
103.
by _chris_ 9y ago
Spectre can be completely mitigated, it's just another headache to deal with. =( Essentially, you just have to buffer up more stuff and clear the misspeculated entries so nothing is left lying around that could leak information. Comes
104.
by _chris_ 9y ago
And RISC-V has a "machine mode" which the OS doesn't know about, which is effectively a place to do microcode.
105.
by _chris_ 9y ago
> synthesizable core That means two things. One, that the design description ("RTL code") can be pushed through synthesis and place-and-route tools and turned into gates. This is useful for putting the design onto an FPGA or
106.
by _chris_ 9y ago
> any open source solution that utilized the same performance strategies would have also had the same attack vector. And then researchers, armed with open-source hardware implementations, can openly probe the systems with white box att
107.
by _chris_ 9y ago
I myself have had little difficulty in debugging Chisel designs using waveforms: virtually every Chisel node has its name maintained in Verilog. Sure, there are many, many more temporary variables created between nodes, but what I care abou
108.
by _chris_ 9y ago
As a RISC-V core implementer, I'm super interested in answers to this question. Some of the things I've pondered is ways to figure out 1) what branch am I constantly mispredicting and 2) what load is constantly cache-missing. Not
109.
by _chris_ 9y ago
Me too!
110.
by _chris_ 9y ago
Of course it's important to always keep the "Iron Law" in mind, but it's far easier to compare ideas and talk about things in terms of IPC. For example, if a switch out one branch predictor for another, we're talkin
111.
by _chris_ 9y ago
> Split up the physical register file so each pipe has it's own fraction of it, and have the register renaming logic "route" to the correct fraction? Have I got the paper for you! From my adviser's previous student:
112.
by _chris_ 9y ago
Sorry to disappoint, AllSeeingEyes. What I taped out is a fairly modest instantiation of BOOM. I was trying to reduce risk and we had a very small area to play with, so I settled for ~4 CM/MHz. One potential win here would have been t
113.
by _chris_ 9y ago
Hi phkahler, the ultimate critical path is the load data coming back to the register file. Replicating the register file doesn't end up being a win (there would be so much area to broadcast it out to), otherwise, everybody would do it.
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by _chris_ 9y ago
WD made it clear in there talk that this wasn't about saving on costs, but rather having control over the innovation in the data space. I don't see any reason to doubt them. It's an incredible risk to switch their entire comp
115.
by _chris_ 9y ago
Actually it is.
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by _chris_ 9y ago
>If you want to make a change to your interview process, give it to some of your current employees first. If anyone fails it, ask yourself if that person should be fired. The answer is probably no. That's a fascinating idea that&#
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by _chris_ 9y ago
Compile RISC-V QEMU or RISC-V Spike simulator on ARM?
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by _chris_ 9y ago
> There is ZERO riscv software at all Exactly. So if you are porting your code to RISC-V don't you want as fast of a simulator as possible?
119.
by _chris_ 9y ago
BOOM is built on top of rocket-chip, both going back to 2011-2012 at Berkeley. The rocket-chip devs graduated Berkeley and started SiFive. SiFive still use, update, and commit back to the rocket-chip code base and have spent resources on ve
120.
by _chris_ 9y ago
While they could easily drop in a BOOM core, there would be some very non-trivial costs for SiFive to verify the IP and tune up the performance and feature set to match their costumers' needs. A lot of work has been put into Rocket onc

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