18 ms·
How AlphaChip transformed computer chip design
- negativeonehalf 2y agoChips are the limiting factor for AI, and now we have AIs making chips better than human engineers. This feels like an infinite compute cheat code, or at least a way to get us very, very quickly to the physical optimum.
- pptr 2y agoIt's 6% shorter wire length. Hardly an infinite compute glitch.
- negativeonehalf 2y ago6% is just the latest one - this is a real-deal engineering task in the chip design process, that an AI can do better than a human expert, and the gap is growing with time. I'm sure there's a limit, but we don't know what it is yet, especially as they hand over more of the chip design process to AI.
- yeahwhatever10 2y agoWhy do they keep saying "superhuman"? Algorithms are used for these tasks, humans aren't laying out trillions of transistors by hand.
- epistasis 2y agoGoogle is good at many things, but perhaps their strongest skill is media positioning.
- jonas21 2y agoI feel like they're particularly bad at this, especially compared to other large companies.
- pinewurst 2y agoFamiliarity breeds contempt. They've been pushing the Google==Superhuman thing since the Internet Boom with declining efficacy.
- deleted 2y ago[deleted]
- lordswork 2y agoThe media hates Google.
- epistasis 2y agoIt a love/hate relationship. Which benefits Google and the media greatly.
- jeffbee 2y agoThis is floorplanning the blocks, not every feature. We are talking dozens to hundreds of blocks, not billions-trillions of gates and wires. I assume that the human benchmark is a human using existing EDA tools, not a guy with a pocket protector and a roll of tape.
- yeahwhatever10 2y agoFloorplanning algorithms and solvers already exist https://limsk.ece.gatech.edu/course/ece6133/slides/floorplanning.pdf https://limsk.ece.gatech.edu/course/ece6133/slides/floorplan...
- jeffbee 2y agoThe original paper from DeepMind evaluates what they are now calling AlphaChip versus existing optimizers, including simulated annealing. They conclude that AlphaChip outperforms them with much less compute and real time. https://www.cl.cam.ac.uk/~ey204/teaching/ACS/R244_2021_2022/papers/Mirhoseini_NATURE_2021.pdf https://www.cl.cam.ac.uk/~ey204/teaching/ACS/R244_2021_2022/...
- foobarian 2y agoRandomized algorithms strike again!
- sudosysgen 2y agoThis is moreso amortized optimization/reinforcement learning, not randomized algorithms.
- hulitu 2y ago> They conclude that AlphaChip outperforms them with much less compute and real time. Of course they do. I'm waiting for their products.
- fph 2y agoMy state-of-art bubblesort implementation is also superhuman at sorting numbers.
- xanderlewis 2y agoNice. Do you offer API access for a monthly fee?
- int0x29 2y agoI'll need 7 5 gigawatt datacenters in the middle of major urban areas or we might lose the Bubble Sort race with the Chinese.
- gattr 2y agoSurely a 1.21-GW datacenter would suffice!
- therein 2y agoHave we decided when are we deprecating it? I'm already cultivating another team in a remote location to work on a competing product that we will include into Google Cloud a month before deprecating this one.
- dgacmu 2y agoSurely you'll be able to reduce this by getting TSMC to build new fabs to construct your new Bubble Sort Processors (BSPs).
- qingcharles 2y agoI'll give you US$7Tn in investment. Just don't ask where it's coming from.
- HPsquared 2y agoNice. Still true though! We are in the bubble sort era of AI.
- jayd16 2y ago"superhuman or comparable" What nonsense! XD
- thomasahle 2y agoBelieve it or not, but there was a time where algorithms were worse than humans at layout out transistors. In particular at the higher level design decisions.
- justsid 2y agoThat’s somewhat still the case, humans could do a much better job at efficient layouting. The problem is that humans don’t scale as well, laying out billions of transistors is hard for humans. But computers can do it if you forego some efficiency by switching to standard cells and then throw compute at the problem.
- negativeonehalf 2y agoPrior to AlphaChip, macro placement was done manually by human engineers in any production setting. Prior algorithmic methods especially struggled to manage congestion, resulting in chips that weren't manufacturable.
- AshamedCaptain 2y ago> macro placement was done manually by human engineers in any production setting To quote certain popular TV series .... Sorry, are you from the past? Do your "production" chips only have a couple dozen macros or what?
- deelowe 2y agoI read the paper. Superhuman is a metric they defined in the paper which has to do with how long it takes a human to do certain tasks.
- anna-gabriella 2y agoDoes this make any sense, really? - Define some common words and then let the media run wild with them. How about we redefine "better" and "revolutionize"? Oh, wait, I think people are doing that already...
- mirchiseth 2y agoI must be old because first thing I thought reading AlphaChip was why is deepmind talking about chips in DEC Alpha :-) https://en.wikipedia.org/wiki/DEC_Alpha https://en.wikipedia.org/wiki/DEC_Alpha.
- mdtancsa 2y agohaha, same!
- sedatk 2y agoI first used Windows NT on a PC with a DEC Alpha AXP CPU.
- lamontcg 2y agoI miss Digital Unix, too (I don't really miss the "Tru64" rebrand...)
- kQq9oHeAz6wLLS 2y agoSame!
- dreamcompiler 2y agoLooks like this is only about placement. I wonder if it can be applied to routing?
- amelius 2y agoExactly what I was thinking. Also: when is this coming to KiCad? :) PS: It would also be nice to apply a similar algorithm to graph drawing (e.g. trying to optimize for human readability instead of electrical performance).
- hinkley 2y agoTSMC made a point of calling out that their latest generation of software for automating chip design has features that allow you to select logic designs for TDP over raw speed. I think that’s our answer to keep Dennard scaling alive in spirit if not in body. Speed of light is still going to matter, so physical proximity of communicating components will always matter, but I wonder how many wins this will represent versus avoiding thermal throttling.
- therealcamino 2y agoEDA software has long allowed trading off power, delay, and area during optimization . But TSMC doesn't produce those tools, as far as I'm aware.
- hinkley 2y agohttps://www.tsmc.com/english/dedicatedFoundry/oip/eda_alliance https://www.tsmc.com/english/dedicatedFoundry/oip/eda_allian... They don’t produce but they are tailored for them just the same. “We have” doesn’t have to mean “we made”. They don’t say it as such here but elsewhere they refer to the IP they can make available, which can also be made in house or cross licensed and still count as “we have”.
- therealcamino 2y agoUsed in that sense, the same software could be called Samsung's and Intel's and any other foundry's, since it is qualified for use with those processes as well. But that's not really the main point I was making, which was that there have been 20+ years of cooperative effort in both process design and EDA software to optimize for power and trade it off against other optimization goals. While there are design and packaging approaches that are only coming into use because of "end of Moore's law, what do we do now" reactions, and some may have power implications, power optimization predates that by a good while.
- mikewarot 2y agoI understand the achievement, but can't square it with my belief that uniform systolic arrays will prove to be the best general purpose compute engine for neural networks. Those are almost trivial to route, by nature.
- ilaksh 2y agoIsn't this already the case for large portions of GPUs? Like, many of the blocks would be systolic arrays? I think the next step is arrays of memory-based compute.
- mikewarot 2y agoImagine a bit level systolic array. Just a sea of LUTs, with latches to allow the magic of graph coloring to remove all timing concerns by clocking everything in 2 phases. GPUs still treat memory as separate from compute, they just have wider bottlenecks than CPUs.
- pfisherman 2y agoQuestions for those in the know about chip design. How are they measuring the quality of a chip design? Does the metric that Google is reporting make sense? Or is it just something to make themselves look good? Without knowing much, my guess is that “quality” of a chip design is multifaceted and heavily dependent on the use case. That is the ideal chip for a data center would look very different from those for a mobile phone camera or automobile. So again what does “better” mean in the context of this particular problem / task.
- q3k 2y agoThis is just floorplanning, which is a problem with fairly well defined quality metrics (max speed and chip area used).
- Drunk_Engineer 2y agoOh man, if only it were that simple. A floorplanner has to guestimate what the P&R tools are going to do with the initial layout. That can be very hard to predict -- even if the floorplanner and P&R tool are from the same vendor.
- Drunk_Engineer 2y agoI have not read the latest paper, but their previous work was really unclear about metrics being used. Researchers trying to replicate results had a hard time getting reliable details/benchmarks out of Google. Also, my recollection is that Google did not even compute timing, just wirelength and congestion; i.e. extremely primitive metrics. Floorplanning/placement/synthesis is a billion dollar industry, so if their approach were really revolutionary they would be selling the technology, not wasting their time writing blog posts about it.
- IshKebab 2y ago> Floorplanning/placement/synthesis is a billion dollar industry Maybe all together, but I don't think automatic placement algorithms are a billion dollar industry. There's so much more to it than that.
- ilaksh 2y agoHow far are we from memory-based computing going from research into competitive products? I get the impression that we are already well passed the point where it makes sense to invest very aggressively to scale up experiments with things like memristors. Because they are talking about how many new nuclear reactors they are going to need just for the AI datacenters.
- HPsquared 2y agoAnd think of the embedded applications.
- sroussey 2y agoThe problem is that the competition (our current von neumann architecture) has billions of dollars of R&D per year invested. Better architectures without the yearly investment train will no longer be better quite quickly. You would need to be 100x to 1000x better in order to pull the investment train onto your tracks. Don’t has been impossible for decades. Even so, I think we will see such a change in my lifetime. AI could be that use case that has a strong enough demand pull to make it happen. We will see.
- ilaksh 2y agoI think it's just ignorance and timidity on the part of investors. Memristor or memory-computing startups are surely the next trend in investing within a few years. I don't think it's necessarily demand or any particular calculation that makes things happen. I think people including investors are just herd animals. They aren't enthusiastic until they see the herd moving and then they want in.
- colesantiago 2y agoA marvellous achievement from DeepMind as usual, I am quite surprised that Google acquired them for a significant discount of $400M, when I would have expected it to be in the range of $20BN, but then again Deepmind wasn’t making any money back then.
- deleted 2y ago[deleted]
- dharma1 2y agoit was very early. probably one of their all time best acquisitions in addition to YouTube. Re:using RL and other types AI assistance for chip design, Nvidia and others are doing this too
- amelius 2y agoCan this be abstracted and generalized into a more generally applicable optimization method?
- loandbehold 2y agoEvery generation of chips is used to design next generation. That seems to be the root of exponential growth in Moore's law.
- bgnn 2y agoThat's wrong. Chip design and Moore's law have nothing to do with each other.
- smaddox 2y agoTo clarify what the parent is getting at: Moore's law is an observation about the density (and, really about the cost) of transistors. So it's about the fabrication process, not about the logic design. Practically speaking, though, maintaining Moore's law would have been economically prohibitive if circuit design and layout had not been automated.
- bgnn 2y agoThat's true. The impact on design is reverse of the post I replied to though. Since we got more density, we had more compute available to automate more, which made it economically viable. Every generation had enough compute to design the next generation. Now the device scaling is stagnated, we have more (financially viable) compute available to us than before (compared to design complexity). This is why this AI generated floorplans become viable I think. I'm not sure if it would have been the same should the device scaling would be continuing at its peak. I want to emphasize the biggest barrier for IC design to the outsiders: prohibitively expensive software licenses. IC design software costs are the much higher than conpute and the production costs, and often similar order of magnitude but definitely higher than engineer salaries. This is because of the monopoly of the 3 big companies (Synopsys, Cadence and Mentor Graphics). What wxcites me the most about stuff like OP isn't AI, everyone is doing that. It's the premise of more competition and even open source tool options. In the good old days companies used to have their im-house tools. They are all sacrificed (and pretty much none made open source) because investors thought it's not a core business, so it's inefficient. Now even Nvidia or Apple have no alternative.
- red75prime 2y agoI hope I'll still be alive when they'll announce AlephZero.
- idunnoman1222 2y agoSo one other designer plus Google is using alpha chip for their layouts? - not sure on that title, call me when amd and nvidia are using it
- kayson 2y agoI'm pretty sure Cadence and Synopsys have both released reinforcement-learning-based placing and floor planning tools. How do they compare...?
- hulitu 2y agoThey don't. You cannot compare reality (Cadence, Synopsys) with hype (Google).
- pelorat 2y agoSo you're basically saying that Google should have used existing tools to layout their chip designs, instead of their ML solution, and that these existing tools would have produced even better chips than the ones they are actually manufacturing?
- dsv3099i 2y agoIt’s more like no one outside of Google has been able to reproduce Google’s results. And not for lack of trying. So if you’re outside of Google, at this moment, it’s vapor.
- hulitu 2y ago> So you're basically saying that Google should have used existing tools to layout their chip designs, instead of their ML solution Did they tested their ML solution ? With real world chips ? Are there any "benchmarks" that show that their chip performs better ?
- RicoElectrico 2y agoSynopsys tools can use ML, but not for the layout itself, rather tuning variables that go into the physical design flow. > Synopsys DSO.ai autonomously explores multiple design spaces to optimize PPA metrics while minimizing tradeoffs for the target application. It uses AI to navigate the design-technology solution space by automatically adjusting or fine-tuning the inputs to the design (e.g., settings, constraints, process, flow, hierarchy, and library) to find the best PPA targets.
- cobrabyte 2y agoI'd love a tool like this for PCB design/layout
- onjectic 2y agoFirst thing my mind went to as well, I’m sure this is already being worked on, I think it would be more impactful than even this.
- bgnn 2y agowhy do you think that?
- bittwiddle 2y agoFar more people / companies are designing PCBs than there are designing custom chips.
- foota 2y agoI think the real value would be in ease of use. I imagine the top N chip creators represent a fair bit of the marginal value in pushing the state of the art forward. E.g., for hobbyists or small shops, there's likely not much value in tiny marginal improvements, but for the big ones it's worth the investment.
- dsv3099i 2y agohttps://www.quilter.ai/ https://www.quilter.ai/
- abc-1 2y agoWhy aren’t they using this technique to design better transformer architectures or completely novel machine learning architectures in general? Are plain or mostly plain transformers really peak? I find that hard to believe.
- jebarker 2y agoBecause chip placement and the design of neural network architectures are entirely different problems, so this solution won't magically transfer from one to the other.
- abc-1 2y agoAnd AlphaGo is trained to play Go? The point is training a model through self play to build neural network architectures. If it can play Go and architect chip placements, I don’t see why it couldn’t be trained to build novel ML architectures.
- jebarker 2y agoSure, they could choose to work on that problem. But why do you think that's a more important/worthwhile problem than chip design or any other problem they might choose to work on? My point was that it's not trivial to make self-play for some other problem work, so given all the problems in the world why did you single our neural network architecture design? Especially since it's not the transformer architecture that is really holding back AI progress.
- abc-1 2y agoRecursive self improvement
- vighneshiyer 2y agoThis work from Google (original Nature paper: https://www.nature.com/articles/s41586-021-03544-w https://www.nature.com/articles/s41586-021-03544-w) has been credibly criticized by several researchers in the EDA CAD discipline. These papers are of interest: - A rebuttal by a researcher within Google who wrote this at the same time as the "AlphaChip" work was going on ("Stronger Baselines for Evaluating Deep Reinforcement Learning in Chip Placement"): http://47.190.89.225/pub/education/MLcontra.pdf http://47.190.89.225/pub/education/MLcontra.pdf - The 2023 ISPD paper from a group at UCSD ("Assessment of Reinforcement Learning for Macro Placement"): https://vlsicad.ucsd.edu/Publications/Conferences/396/c396.pdf https://vlsicad.ucsd.edu/Publications/Conferences/396/c396.p... - A paper from Igor Markov which critically evaluates the "AlphaChip" algorithm ("The False Dawn: Reevaluating Google's Reinforcement Learning for Chip Macro Placement"): https://arxiv.org/pdf/2306.09633 https://arxiv.org/pdf/2306.09633 In short, the Google authors did not fairly evaluate their RL macro placement algorithm against other SOTA algorithms: rather they claim to perform better than a human at macro placement, which is far short of what mixed-placement algorithms are capable of today. The RL technique also requires significantly more compute than other algorithms and ultimately is learning a surrogate function for placement iteration rather than learning any novel representation of the placement problem itself. In full disclosure, I am quite skeptical of their work and wrote a detailed post on my website: https://vighneshiyer.com/misc/ml-for-placement/ https://vighneshiyer.com/misc/ml-for-placement/
- s-macke 2y agoWhen I first read about AlphaChip yesterday, my first question was how it compares to other optimization algorithms such as genetic algorithms or simulated annealing. Thank you for confirming that my questions are valid.
- gdiamos 2y agoCriticism is an important part of the scientific process. Whichever approach ends up winning is improved by careful evaluation and replication of results
- jeffbee 2y agoIt seems like this is multiple parties pursuing distinct arguments. Is Google saying that this technique is applicable in the way that the rebuttals are saying it is not? When I read the paper and the update I did not feel as though Google claimed that it is general, that you can just rip it off and run it and get a win. They trained it to make TPUs, then they used it to make TPUs. The fact that it doesn't optimize whatever "ibm14" is seems beside the point.
- lordswork 2y agoSome interesting context on this work: 2 researchers were bullied to the point of leaving Google for Anthropic by a senior researcher (who has now been terminated himself): https://www.wired.com/story/google-brain-ai-researcher-fired-tension/ https://www.wired.com/story/google-brain-ai-researcher-fired... They must feel vindicated by their work turning out to be so fruitful now.
- clickwiseorange 2y agoIt's actually not clear who was bullied. The two researchers ganged up on Chatterjee and got him fired because he used the word "fraud" - wrongful termination of a whistleblower. Only recently Google settled with Chatterjee for an undisclosed amount.
- gabegobblegoldi 2y agoVindicated indeed. The senior researcher and others on the project were bullied for raising concerns of fraud by the two researchers [1]. They filed a lawsuit against Google that has a lot of detailed allegations of fraud [2]. [1] https://www.theregister.com/AMP/2023/03/27/google_ai_chip_paper_nature/ https://www.theregister.com/AMP/2023/03/27/google_ai_chip_pa... [2] https://regmedia.co.uk/2023/03/26/satrajit_vs_google.pdf https://regmedia.co.uk/2023/03/26/satrajit_vs_google.pdf
- negativeonehalf 2y agoYou are now using multiple new accounts based on the name of one of the authors (Anna Goldie) and her husband (Gabriel). First this one ('gabegobblegoldi'), and then 'anna-gabriella'. I think it is time for you to take a deep breath and think about what you are doing and why. You seem to be obsessed with the idea that this work is overrated. MediaTek and Google don't think so, and use it in production for their chips, including TPU, Dimensity, Axion, and others. If you're right and they're wrong, using this method loses them money. If it's the other way around, then using this method makes them gain money. Please read PG's post and ask yourself if it applies to you: https://www.paulgraham.com/fh.html https://www.paulgraham.com/fh.html Chatterjee settled his case. He has moved on. This is not some product being sold -- it is a free, open-source tool. People who see value in it use it; others don't, and so they don't. This is how it always works, and it's fine.
- FrustratedMonky 2y agoSo AI designing it's own chips. Now that is moving towards exponential growth. Like at the end of "Colossus" the movie. Forget LLM's. What DeepMind is doing seems more like how an AI will rule, in the world. Building real world models, and applying game logic like winning. LLM's will just be the text/voice interface to what DeepMind is building.
- anna-gabriella 2y agoI can tell you get excited by SciFi, that's where Google's work belongs - people have been unable to reproduce it outside Google by a long shot.
- FrustratedMonky 2y agoAlpha-GO was not sci-fi. And that was 2016 Protein Folding? That was against a defined data set and other organizations. Nobody can re-produce? Isn't that the definition of a competitive advantage? They are building something others can't, and that is bad? That is what companies do.
- anna-gabriella 2y agoWe are discussing AlphaChip in 2024, not AlphaGo from 2016. I don't know much about protein folding (there were some controversies there, but that's not relevant). Neither of these has been related to product claims. As for "nobody can re-produce", no, that's not the definition. Imaginary things are not competitive advantage. They are exaggerating, and that's bad. But yeah, that's what companies do, you are right.
- FrustratedMonky 2y ago"Imaginary things" I get the impression you just aren't keeping up with DeepMind. They have made huge break throughs in science, and they publish their results in Nature. Just because the parent company Google had some bad demo's doesn't mean it is all bunk. So guess if you are of the ilk that just doesn't trust anything anymore, that there is no peer reviews, all science is a fraud. I really can't help that.
- DrNosferatu 2y agoYet, their “frontier” LLM lags all the others…
- deleted 2y ago[deleted]
- 7e 2y agoDid it, though? Google’s chips still aren’t very good compared with competitors.
- ninetyninenine 2y agoWhat occupation is there that is purely intellectual that has no chance of an AI ever progressing to a point where it can take it over?
- alexyz12 2y agoanything that needs very real-time info. AI's will always be limited by us feeding them info, or them collecting it themselves. But humans can travel to more places than an AI can, until robots are everywhere too I suppose
- Zamiel_Snawley 2y agoI think only sentimentality can prevent take over by a sufficiently competent AI. I don’t want art that wasn’t made by a human, no matter how visually stunning or indistinguishable it is.
- ninetyninenine 2y agoDiscounting fraud... what if the AI produces something genuinely better. Genuinely moving you to tears? What then? Imagine your favorite movie, the most moving book. You read it, it changed you, then you found out it was an AI that generated it in a mere 10 seconds. Artificial sentimentality is useless in the face of reality. That human endeavor is simply data points along an multi-dimensional best fit curve.
- Zamiel_Snawley 2y agoThat’s a challenging hypothetical. I think it would feel hollowed out, disingenuous. It feels too close to being a rat with a dopamine button, meaningless hedonism. I haven’t thought it through particularly thoroughly though, I’d been interested in hearing other opinions. These philosophical questions quickly approach unanswerable.
- ninetyninenine 2y ago>These philosophical questions quickly approach unanswerable. With the current trendline of AI progress in the last decade the question has a high possibility of being answered by being actualized in reality. It's not a random question either. With AI quickly entrenching itself into every aspect of human creation from art, music, to chip design, this is all I can think about.
- QuadrupleA 2y agoHow good are TPUs in comparison with state of the art Nvidia datacenter GPUs, or Groq's ASICs? Per watt, per chip, total cost, etc.? Is there any published data?
- jeffbee 2y agoMLPerf is a good place to start. The only problem is you don't have any verifiable information about TPU energy consumption. https://mlcommons.org/benchmarks/inference-datacenter/ https://mlcommons.org/benchmarks/inference-datacenter/
- wslh 2y agoI have some company notes from early 2024 which cannot be accurate but could help, TPU v5e [1]: not available for purchase, only through GCP, storage=5B, LLM-Model=7B, efficiency=393TFLOP. [1] https://cloud.google.com/tpu/docs/v5e https://cloud.google.com/tpu/docs/v5e
- ur-whale 2y agoSeems to me the article is claiming a lot of things, but is very light on actual comparisons that matter to you and me, namely: how does one of those fabled AI-designed chop compare to their competition ? For example, how much better are these latest gen TPU's when compared to NVidia's equivalent offering ?
- gabegobblegoldi 2y agoGood question. I thought the tpus were a way for Google to apply pricing pressure to nvidia by having an alternative. They are not particularly better (it’s hard to get utilization), and I believe Google continues to be a big buyer of nvidia chips.
- thesz 2y agoEurisco [1], if I remember correctly, was once used to perform placement-and-route task and was pretty good at it. [1] https://en.wikipedia.org/wiki/Eurisko https://en.wikipedia.org/wiki/Eurisko What's more, Eurisco was then used in designing Traveler TCS' game fleet of battle spaceships. And Eurisco used symmetry-based placement learned from VLSI design in the design of the spaceships' fleet. Can AlphaChip's heuistics be used anywhere else?
- gabegobblegoldi 2y agoDoesn’t look like it. In fact the original paper claimed that their RL method could be used for all sorts of combinatorial optimization problems. Yet they chose an obscure problem in chip design and showed their results on proprietary data instead of standard public benchmarks. Instead they could have demonstrated their amazing method on any number of standard NP hard optimization problems e.g. traveling salesman, bin packing, ILP, etc. where we can generate tons of examples and verify easily whether it produces better results than other solvers or not. This is why many in the chip design and optimization community felt that the paper was suspicious. Even with this addendum they adamantly refuse to share any results that can be independently verified.
- AshamedCaptain 2y ago> Yet they chose an obscure problem in chip design It is not obscure (in chip design). If anything it is one of the most easily reachable problems. Almost every other PhD student in the field has implemented a macro placer, even if just for fun, and there are frequent academic competitions. A lot of design houses also roll their own macro placers since it's not a difficult problem and generally adding a bit of knowledge of your design style can help you gain an extra % over the generic commercial tools. It does not surprise me at all that they decided to start with this for their foray into chip EDA. It's the minimum effort route.
- gabegobblegoldi 2y agoSorry. I meant obscure relative to the large space of combinatorial optimization problems not just chip design. Most design houses don’t write their own macro placers but customize commercial flows for their designs. The problem with macro placement as an RL technology demonstrator is that to evaluate quality you need to go through large parts of the design flow which involves using other commercial tools. This makes it incredibly hard to evaluate superiority since all those steps and tools add noise. Easier problems would have been to use RL to minimize the number of gates in a logic circuit or just focus on placement with half perimeter wirelength (I think this is what you mean with your grad student example). Essentially solving point problems in the design flow and evaluating quality improvements locally. They evaluated quality globally and only globally and that destroys credibility in this business due to the noise involved unless you have lots of examples, can show statistical significance, and (unfortunately for the authors) also local improvements. That’s what the follow on studies did and that’s why the community has lost faith in this particular algorithm.
- AshamedCaptain 2y agoWhat is Google doing here? At best, the quality of their "computer chip design" work can be described as "controversial" https://spectrum.ieee.org/chip-design-controversy https://spectrum.ieee.org/chip-design-controversy . What is there to gain by just making a PR now without doing anything new?
- negativeonehalf 2y agoIn the blog post, they announce MediaTek's widespread usage, the deployment in multiple generations of TPU with increasing performance each generation, Axion, etc. Chips designed with the help of AlphaChip are in datacenters and Samsung phones, right now. That's pretty neat!
- sijnapq 2y ago[dead]
- bankcust08385 2y agoTechnology singularity is around the corner as soon as the chips (mostly) design themselves. There will be a few engineers, zillions of semiskilled maintenance people making a pittance, and most of the world will be underemployed or unemployed. Technical people better understand this and unionize or they will find themselves going the way of piano tuners and Russian physicists. Slow boiling frog...
- bachback 2y agoDeepmind is producing science vapourware while OpenAI is changing the world
- Upvoter33 2y agoTo me, there is an underlying issue: why are so many DeepX papers being sent to Nature, instead of appropriate CS forums? If you are doing better work in chip design, send it to IPSD or ISCA or whatever, and then you will get the types of reviews needed for this work. I have no idea what Nature does with a paper like this.
- negativeonehalf 2y agoThere's a lot of... passionate discussion in this thread, but we shouldn't lose sight of the big picture -- Google has used AlphaChip in multiple generations of TPU, their flagship AI accelerator. This is a multi-billion dollar project that is strategically critical for the success of the company. The idea that they're secretly making TPUs worse in order to prop up a research paper is just absurd. Google has even expanded their of AlphaChip use to other chips (e.g. Axion). Meanwhile, MediaTek built on AlphaChip and is using it widely, and announced that it was used to help design Dimensity 5G (4nm technology node size). I can understand that, when this open-source method first came out, there were some who were skeptical, but we are way beyond that now -- the evidence is just overwhelming. I'm going to paste here the quotes from the bottom of the blog post, as it seems like a lot of people have missed them: “AlphaChip’s groundbreaking AI approach revolutionizes a key phase of chip design. At MediaTek, we’ve been pioneering chip design’s floorplanning and macro placement by extending this technique in combination with the industry’s best practices. This paradigm shift not only enhances design efficiency, but also sets new benchmarks for effectiveness, propelling the industry towards future breakthroughs.” --SR Tsai, Senior Vice President of MediaTek “AlphaChip has inspired an entirely new line of research on reinforcement learning for chip design, cutting across the design flow from logic synthesis to floor planning, timing optimization and beyond. While the details vary, key ideas in the paper including pretrained agents that help guide online search and graph network based circuit representations continue to influence the field, including my own work on RL for logic synthesis. If not already, this work is poised to be one of the landmark papers in machine learning for hardware design.” --Siddharth Garg, Professor of Electrical and Computer Engineering, NYU "AlphaChip demonstrates the remarkable transformative potential of Reinforcement Learning (RL) in tackling one of the most complex hardware optimization challenges: chip floorplanning. This research not only extends the application of RL beyond its established success in game-playing scenarios to practical, high-impact industrial challenges, but also establishes a robust baseline environment for benchmarking future advancements at the intersection of AI and full-stack chip design. The work's long-term implications are far-reaching, illustrating how hard engineering tasks can be reframed as new avenues for AI-driven optimization in semiconductor technology." --Vijay Janapa Reddi, John L. Loeb Associate Professor of Engineering and Applied Sciences, Harvard University “Reinforcement learning has profoundly influenced electronic design automation (EDA), particularly by addressing the challenge of data scarcity in AI-driven methods. Despite obstacles including delayed rewards and limited generalization, research has proven reinforcement learning's capability in complex electronic design automation tasks such as floorplanning. This seminal paper has become a cornerstone in reinforcement learning-electronic design automation research and is frequently cited, including in my own work that received the Best Paper Award at the 2023 ACM Design Automation Conference.” --Professor Sung-Kyu Lim, Georgia Institute of Technology "There are two major forces that are playing a pivotal role in the modern era: semiconductor chip design and AI. This research charted a new path and demonstrated ideas that enabled the electronic design automation (EDA) community to see the power of AI and reinforcement learning for IC design. It has had a seminal impact in the field of AI for chip design and has been critical in influencing our thinking and efforts around establishing a major research conference like IEEE LLM-Aided Design (LAD) for discussion of such impactful ideas." --Ruchir Puri, Chief Scientist, IBM Research; IBM Fellow