10 ms·

Intel, Samsung, and TSMC Demo 3D-Stacked Transistors

329 points by jnord 3y ago

kosasbest 3y ago
Interesting that when we can't make chips bigger laterally, we go vertical and stack transistors. It's like we discovered high-rise buildings all over again.
ChuckMcM 3y ago
Fun times. I think one of the interesting takeaways here should be that they have a 48 - 50nm "device pitch" which is to say the transistors are small in the XY plane there are pitch widths much larger than "5nm" or "3nm" (people familiar with chip production realize this but too often people who don't have a very deep understanding of chip production are mislead into thinking you can put down transistors 5nm apart from each other) So from a density perspective, a perhaps 30 - 40% gain in overall number of transistors in the same space. Looking at the Intel inverter design, it looks like if they were willing to double the depth they could come up with a really compact DRAM cell. A chiplet with 8 GB of ECC DDR memory on it would be a useful thing both for their processors and their high end FPGA architectures.
- markhahn 3y ago
  really compact DRAM? have you seen DRAM? the aspect ratio is already huge, though afaik no one stacks the pass transistor. high-end systems already have stacked DRAM chiplets, though admittedly this hasn't made much of an appearance outside GPUs until now (MI300a).
andrewstuart 3y ago
What real world outcomes might we expect from this technology? Anyone know?
- thunderbird120 3y ago
  Faster chips which use less power to do the same amount of computation, same as ever. CFETs are very much real world technology which are on the roadmaps for all leading edge fabs. They're the same as current gen FinFets and GAAFets a year or two from now in that they essentially just do the same thing as previous generations of chip tech except they do it better.
- WaxProlix 3y ago
  Novel cooling solutions, among others, one suspects.
  - CyberDildonics 3y ago
    What do you mean by that and what are you basing that on?
    - WaxProlix 3y ago
      Running watts through transistors produces heat. Flat transistors are cooled by various heat dispersal mechanisms today. Thicker 3D stacked transistors will possibly provide impetus for a different cooling paradigm.
      - CyberDildonics 3y ago
        This is just the same thing you said before worded differently. What different cooling paradigm and what information leads you to think that it's a reality?
        WaxProlix 3y ago
        I think you've missed the point, sorry.
- amelius 3y ago
  Thicker phones.
  - Narishma 3y ago
    One can dream.
dcreater 3y ago
Since it's still a GAA channel, are the channel lengths sthr same as the latest 3nm node?
29athrowaway 3y ago
What does heat do in these chips? How does it not melt?
- markhahn 3y ago
  heat density is heat density. this technique isn't the same as stacking two logic dies (which would have a heat problem). backside power is actually a pretty important power improvement - both delivery and cooling.
bogtog 3y ago
General question about semiconductors: Why is there so much emphasis on the density of transistors rather than purely on the costs of production (compute/$)? CPUs aren't particularly large. My computer's CPU may be just a few tablespoons in volume. Hence, is compute less useful if it's spread out (e.g., due to communication speeds)?
- nsonha 3y ago
  the physical limitation of more CPUs: heat, which in turn downgrades performance
  - mikepurvis 3y ago
    But I think the GP's point is that heat is far easier managed when spread out over a larger area, so why all the emphasis on ultra tiny transistors vs just making a chip that's two inches by two inches or something? And I think the main answer to that comes when you look at some of the discourse around Apple's M-series chips, that doing a larger-die design is just way riskier: there are huge implications on cost, yield, flexibility, etc, so it was really something that Apple was uniquely positioned to move aggressively on vs a player like Qualcomm who needs to be way more conservative in what they try to sell to their main customers (phone OEMs like Samsung).
    - dist-epoch 3y ago
      > making a chip that's two inches by two inches These already exist. Lookup images of AMD Ryzen Threadripper PRO 7995WX - 96 cores: https://www.techpowerup.com/img/fp51OPD4JRS7wvTK.jpg https://www.techpowerup.com/img/fp51OPD4JRS7wvTK.jpg
      - dontlaugh 3y ago
        Those are made up of much smaller chiplets. No individual die is all that big
        3y ago
tambourine_man 3y ago
It’s fun to be just a curious bystander for many years in this industry. Every now and then Moore’s law hits a roadblock. Some experts see that as a clear sign that it’s reaching its end. Others that it’s already dead, because actually, the price per transistor has increased. Others that it’s physics, we can approach Y but after X nm it can’t be done. Then you read others that claim that Intel has just been lazy enjoying its almost monopoly for the past decade and was caught off guard by TSMC’s ultraviolet prowess. Or people who really know how the sausage is made, like Jim Keller, enthusiastically stating that we are nowhere near any major fundamental limitation and can expect 1000X improvement in the years to come at least. Anyway, it’s really fun to watch, like I said. Hard to think of a field with such rollercoaster-like forecasting while still delivering unparalleled growth in such a steady state for decades.
- zozbot234 3y ago
  The limitations are very real. Dennard scaling has been dead since the mid-2000s (that is, power use per unit area has been increasing, even though energy use per logic operation is very much dropping at leading edge nodes) which means an increasing fraction of all silicon has to be "dark", power-gated and only used for the rare accelerated workload. Additionally, recent nodes have seen very little improvement in SRAM cell size which is used for register files and caches. So perhaps we'll be seeing relatively smaller caches per core in the future, and the addition of eDRAM (either on-die or on a separate chiplet) as a new, slower L4 level to partially cope with that.
  - mikepurvis 3y ago
    What if it went the other way and you got much larger die area dedicated to caches or even on-chip RAM, since that usage is relatively cheaper from a power/heat point of view? Or is the process different enough between the two that it just doesn't make sense to have them interwoven like that?
    - adgjlsfhk1 3y ago
      the caches are already ~75% of the space. you can't significantly increase that. On die ram is also relatively unlikely due to process differences. my best guess is more 3d cache chips. if we can get the interconnects small enough and fast enough, I could see a future where the logic is stacked on top of a dozen (physical) layers of stacked cache
0x1ceb00da 3y ago
Is that going to increase the GHz as well or just the number of cores.
- rishav_sharan 3y ago
  Doubt that. Frequency will be tied to heat dissipation. And in a 3d stack, the heat dissipation of the inner transistors is going to be very difficult
  - sundvor 3y ago
    In gaming, especially simulators: The 5800x3d and then the 7800x3d has proved how exemplary performance benefits can be gained in certain use cases, in some cases outperforming Intel with less than half the power usage (if not a third). Limiting overclocking is a price to pay for that, but you kind of get it back with the monthly power bills - and still going toe to toe with Intel in general.
    - DeathArrow 3y ago
      I doubt that for one user using one CPU the power bill is going to matter. People still use AC, washing machines and electrical heating consuming thousands of kw.
      - sundvor 3y ago
        It's a 100-150w difference. It all adds up. This also means you don't need to run the fans in your system as high.
        markhahn 3y ago
        Look at the numbers. Power/heat matters for datacenters, but not for people. Yes, you can built a kw desktop, but you know you're doing something weird. For most people, their computer's peak dissipation has been falling for a decade. 90W cpus used to be common, but mainstream is currently going from 65 to 40W categories in desktops. And normal people do not have GPUs. Even more normal people depend primarily on mobile devices, where 15W laptops are routine, and lots of people use devices <4W.
sh1mmer 3y ago
Maybe I’m missing something here, but wouldn’t heat become a bigger issue? Right now we have pretty intense cooling solutions to get heat off the surface of a comparatively thinner chip. If chips become more cubic how would we cool the inside?
- TOMDM 3y ago
  If we keep going down this route I have to wonder if we'll see something drastic in the cooling space. CPU dies are optimised towards being cooled from one side. I wonder if we'll eventually see sockets, motherboards and heat spreaders shift towards cooling both sides of the CPU. Probably not, can't imagine what a halfway feasible solution to integrating pin out and a heat spreader would be.
  - teaearlgraycold 3y ago
    A relatively easy win here is to have a “stock” set of fins built into the motherboard behind the CPU socket. The CPU could get attached to it with a pad or paste on the back.
  - mook 3y ago
    A couple years back they noted that they were looking at having essentially cooling pipes _inside_ the chips. There hasn't been much noise in terms of commercialization, but that's the kind of extreme they were looking at. https://www.tomshardware.com/news/tsmc-exploring-on-chip-semiconductor-integrated-watercooling https://www.tomshardware.com/news/tsmc-exploring-on-chip-sem...
  - dist-epoch 3y ago
    > cooling both sides of the CPU That would only double cooling capacity, and has costs - completely invalidates current motherboard designs.
  - chainingsolid 3y ago
    Heres my first thought on how you might be able to do pin out on a 'sandwich a cpu between 2 heatsinks design'. 1) DRAM gets integrated with the cpu. Slight thickness increase, probably quite a bit of added width. We get a bigger area to cool, closer ram and no need for any memory pins. 2) Add power connections to the 2 cooling sides. Running power wires through the coolers shouldn't be an issue. 3) Run as many of the fastest PCIe lanes as you can out the 4 thin sides of the package. These end up handling ALL of the IO. Some downsides I can think of off the bat are cooking the ram chips and with so much density and heat not sure how well signal integrity would work out.
cubefox 3y ago
> Experts estimate CFETs to roll out commercially seven to ten years from now, but there is still a lot of work before they are ready. So the technology is still very much science fiction at this point.
- deleted 3y ago
  [deleted]
- smolder 3y ago
  No, they've been made, just not via scaled-up commercial production process.
  - cubefox 3y ago
    The fact that they are predicted to be "seven to ten years" away suggests there are still many unsolved problems that are preventing scaling-up from becoming a reality.
    - smolder 3y ago
      Fair point. I think for comparison it's interesting that Intel spent most of a decade on a single process.
oldesthacker 3y ago
Interesting bit about Samsung’s secret sauce: Samsung went even smaller than Intel, showing results for 48-nm and 45-nm contacted poly pitch (CPP), compared to Intel’s 60 nm, though these were for individual devices, not complete inverters. Although there was some performance degradation in the smaller of Samsung’s two prototype CFETs, it wasn’t much, and the company’s researchers believe manufacturing process optimization will take care of it. Crucial to Samsung’s success was the ability to electrically isolate the sources and drains of the stacked pFET and nFET devices. Without adequate isolation, the device, which Samsung calls a 3D stacked FET (3DSFET), will leak current. A key step to achieving that isolation was swapping an etching step involving wet chemicals with a new kind of dry etch. That led to an 80 percent boost in the yield of good devices. Like Intel, Samsung contacted the bottom of the device from beneath the silicon to save space. However, the Korean chipmaker differed from the American one by using a single nanosheet in each of the paired devices, instead of Intel’s three. According to its researchers, increasing the number of nanosheets will enhance the CFET’s performance.
- deleted 3y ago
  [deleted]
KingLancelot 3y ago
[dead]
anthk 3y ago
Any EE member here? How's photonics' computing going?
drtgh 3y ago
In storage, moving away from 2D MLC and TLC NAND towards 3D TLC stacking (and horrendous higher bits) has introduced disturbances that literally shorten the memory life cycle. When a cell is read, the voltage alters the state of adjacent cells, which must be forced to be rewritten to preserve their state, thus shortening the life cycle of the disk just by reading data. they are selling us crap. From the little I understand about the problem, this would be solved by occupying more surface area to separate the tracks that run through the vertical stacks ? what would be like a 2D design surface area but with bigger complications. Although I have read papers[1] that propose adding latency in an attempt to mitigate (not solve) the problem. So now, reading this news about processors and stacking, I wonder about what inconveniences the end users are going to suffer with processors built under these techniques. Whether in computational reliability, vulnerabilities and so on. I wrote vulnerabilities (pure imagination and speculation of my own, I'm imagining a prefetch problem at the transistor level) because if it turns to be real at future I can see the manufacturer introducing a fix for randomly increase latencies or any other thing, and sending the computing power back ten years with an "oh, we didn't expect it such thing were possible when we designed it". And of course the computational reliability. is being taken care of to avoid all of this?.. if not, I leave my comment here for courts in the future. [1] [2021] doi.org/10.1145/3445814.3446733 (use sci-hub) [2] [2018] doi.org/10.1145/3224432 https://people.inf.ethz.ch/omutlu/pub/3D-NAND-flash-lifetime-early-retention-loss-and-process-variation_sigmetrics18_pomacs18-twocolumn.pdf https://people.inf.ethz.ch/omutlu/pub/3D-NAND-flash-lifetime...
- FirmwareBurner 3y ago
  >So now, reading this news about processors and stacking, I wonder about what inconveniences the end users are going to suffer with processors built under these techniques. Whether in computational reliability, vulnerabilities and so on. Denser logic hasn't got the same issues as dense non-volatile storage as logic doesn't need to have any persistence. It's what the likes of Micron and Samsung are good at fixing and working around when they launch and scale their Xnm processes for a specific storage technology, and what makes them better than competitors. Intel, TSMC, GloFo, etc they all can buy the latest gen EUV machines from ASML if they want, but yet TSMC is always one node ahead on logic and Micron and Samsung win at storage, because they're good at ironing out the kinks and challenges that come from shrinking down those specific designs closer and closer to sub-nm level while the others can not (so easily). If fabbing cutting edge silicone was as easy as just having the latest gen ASML machines, then ASML would just hoard the cutting edge machines for themselves and become vertically integrated in fabbing their own cutting chips as a side hustle before everyone else.
CalChris 3y ago
A minor startup isn't Intel, Samsung and TSMC but www.thruchip.com did 3d stacking 10 years ago. https://web.stanford.edu/class/ee380/Abstracts/141022-slides.pdf https://web.stanford.edu/class/ee380/Abstracts/141022-slides... https://www.theregister.com/2014/02/21/thruchip_communications_comes_up_with_alternative_to_through_silicon_vias/ https://www.theregister.com/2014/02/21/thruchip_communicatio...
- baybal2 3y ago
  [dead]
- markhahn 3y ago
  the case for inductive stacked chips is pretty compelling, if those slides are right! I wonder if you can also couple adjacent chips that way, since 2.5D is, if anything, more important than stacking...
coreyh14444 3y ago
From the Terminator fandom wiki: The CPU was modeled and designed primarily on computers in advanced 3-Dimensional programming packages, where simulated testing could be done in real time, or at increased rates. The lattice of cubes in the construction of the prototype CPU suggests a "hypercube", a cube of more than three dimensions. In computer design, hypercubes are used as a physical connection scheme that minimizes the effective communication distance (and therefore the time delay) between processors, when the logical connection scheme needed by the software that will be run on those processors cannot be known in advance. This then supports the Neural Net's ability to learn, adapt, and built new logical connection schemes.

329 points by jnord 3y ago

Interesting that when we can't make chips bigger laterally, we go vertical and stack transistors. It's like we discovered high-rise buildings all over again.

ChuckMcM 3y ago

Fun times. I think one of the interesting takeaways here should be that they have a 48 - 50nm "device pitch" which is to say the transistors are small in the XY plane there are pitch widths much larger than "5nm" or "3nm" (people familiar with chip production realize this but too often people who don't have a very deep understanding of chip production are mislead into thinking you can put down transistors 5nm apart from each other) So from a density perspective, a perhaps 30 - 40% gain in overall number of transistors in the same space. Looking at the Intel inverter design, it looks like if they were willing to double the depth they could come up with a really compact DRAM cell. A chiplet with 8 GB of ECC DDR memory on it would be a useful thing both for their processors and their high end FPGA architectures.

markhahn 3y ago
really compact DRAM? have you seen DRAM? the aspect ratio is already huge, though afaik no one stacks the pass transistor. high-end systems already have stacked DRAM chiplets, though admittedly this hasn't made much of an appearance outside GPUs until now (MI300a).

andrewstuart 3y ago

What real world outcomes might we expect from this technology? Anyone know?

thunderbird120 3y ago
Faster chips which use less power to do the same amount of computation, same as ever. CFETs are very much real world technology which are on the roadmaps for all leading edge fabs. They're the same as current gen FinFets and GAAFets a year or two from now in that they essentially just do the same thing as previous generations of chip tech except they do it better.
WaxProlix 3y ago
Novel cooling solutions, among others, one suspects.
- CyberDildonics 3y ago
  What do you mean by that and what are you basing that on?
  - WaxProlix 3y ago
    Running watts through transistors produces heat. Flat transistors are cooled by various heat dispersal mechanisms today. Thicker 3D stacked transistors will possibly provide impetus for a different cooling paradigm.
    - CyberDildonics 3y ago
      This is just the same thing you said before worded differently. What different cooling paradigm and what information leads you to think that it's a reality?
      - WaxProlix 3y ago
        I think you've missed the point, sorry.
amelius 3y ago
Thicker phones.
- Narishma 3y ago
  One can dream.

dcreater 3y ago

Since it's still a GAA channel, are the channel lengths sthr same as the latest 3nm node?

29athrowaway 3y ago

What does heat do in these chips? How does it not melt?

markhahn 3y ago
heat density is heat density. this technique isn't the same as stacking two logic dies (which would have a heat problem). backside power is actually a pretty important power improvement - both delivery and cooling.

bogtog 3y ago

General question about semiconductors: Why is there so much emphasis on the density of transistors rather than purely on the costs of production (compute/$)? CPUs aren't particularly large. My computer's CPU may be just a few tablespoons in volume. Hence, is compute less useful if it's spread out (e.g., due to communication speeds)?

nsonha 3y ago
the physical limitation of more CPUs: heat, which in turn downgrades performance
- mikepurvis 3y ago
  But I think the GP's point is that heat is far easier managed when spread out over a larger area, so why all the emphasis on ultra tiny transistors vs just making a chip that's two inches by two inches or something? And I think the main answer to that comes when you look at some of the discourse around Apple's M-series chips, that doing a larger-die design is just way riskier: there are huge implications on cost, yield, flexibility, etc, so it was really something that Apple was uniquely positioned to move aggressively on vs a player like Qualcomm who needs to be way more conservative in what they try to sell to their main customers (phone OEMs like Samsung).
  - dist-epoch 3y ago
    > making a chip that's two inches by two inches These already exist. Lookup images of AMD Ryzen Threadripper PRO 7995WX - 96 cores: https://www.techpowerup.com/img/fp51OPD4JRS7wvTK.jpg https://www.techpowerup.com/img/fp51OPD4JRS7wvTK.jpg
    - dontlaugh 3y ago
      Those are made up of much smaller chiplets. No individual die is all that big
      - 3y ago

tambourine_man 3y ago

It’s fun to be just a curious bystander for many years in this industry. Every now and then Moore’s law hits a roadblock. Some experts see that as a clear sign that it’s reaching its end. Others that it’s already dead, because actually, the price per transistor has increased. Others that it’s physics, we can approach Y but after X nm it can’t be done. Then you read others that claim that Intel has just been lazy enjoying its almost monopoly for the past decade and was caught off guard by TSMC’s ultraviolet prowess. Or people who really know how the sausage is made, like Jim Keller, enthusiastically stating that we are nowhere near any major fundamental limitation and can expect 1000X improvement in the years to come at least. Anyway, it’s really fun to watch, like I said. Hard to think of a field with such rollercoaster-like forecasting while still delivering unparalleled growth in such a steady state for decades.

zozbot234 3y ago
The limitations are very real. Dennard scaling has been dead since the mid-2000s (that is, power use per unit area has been increasing, even though energy use per logic operation is very much dropping at leading edge nodes) which means an increasing fraction of all silicon has to be "dark", power-gated and only used for the rare accelerated workload. Additionally, recent nodes have seen very little improvement in SRAM cell size which is used for register files and caches. So perhaps we'll be seeing relatively smaller caches per core in the future, and the addition of eDRAM (either on-die or on a separate chiplet) as a new, slower L4 level to partially cope with that.
- mikepurvis 3y ago
  What if it went the other way and you got much larger die area dedicated to caches or even on-chip RAM, since that usage is relatively cheaper from a power/heat point of view? Or is the process different enough between the two that it just doesn't make sense to have them interwoven like that?
  - adgjlsfhk1 3y ago
    the caches are already ~75% of the space. you can't significantly increase that. On die ram is also relatively unlikely due to process differences. my best guess is more 3d cache chips. if we can get the interconnects small enough and fast enough, I could see a future where the logic is stacked on top of a dozen (physical) layers of stacked cache

0x1ceb00da 3y ago

Is that going to increase the GHz as well or just the number of cores.

rishav_sharan 3y ago
Doubt that. Frequency will be tied to heat dissipation. And in a 3d stack, the heat dissipation of the inner transistors is going to be very difficult
- sundvor 3y ago
  In gaming, especially simulators: The 5800x3d and then the 7800x3d has proved how exemplary performance benefits can be gained in certain use cases, in some cases outperforming Intel with less than half the power usage (if not a third). Limiting overclocking is a price to pay for that, but you kind of get it back with the monthly power bills - and still going toe to toe with Intel in general.
  - DeathArrow 3y ago
    I doubt that for one user using one CPU the power bill is going to matter. People still use AC, washing machines and electrical heating consuming thousands of kw.
    - sundvor 3y ago
      It's a 100-150w difference. It all adds up. This also means you don't need to run the fans in your system as high.
      - markhahn 3y ago
        Look at the numbers. Power/heat matters for datacenters, but not for people. Yes, you can built a kw desktop, but you know you're doing something weird. For most people, their computer's peak dissipation has been falling for a decade. 90W cpus used to be common, but mainstream is currently going from 65 to 40W categories in desktops. And normal people do not have GPUs. Even more normal people depend primarily on mobile devices, where 15W laptops are routine, and lots of people use devices <4W.

sh1mmer 3y ago

Maybe I’m missing something here, but wouldn’t heat become a bigger issue? Right now we have pretty intense cooling solutions to get heat off the surface of a comparatively thinner chip. If chips become more cubic how would we cool the inside?

TOMDM 3y ago
If we keep going down this route I have to wonder if we'll see something drastic in the cooling space. CPU dies are optimised towards being cooled from one side. I wonder if we'll eventually see sockets, motherboards and heat spreaders shift towards cooling both sides of the CPU. Probably not, can't imagine what a halfway feasible solution to integrating pin out and a heat spreader would be.
- teaearlgraycold 3y ago
  A relatively easy win here is to have a “stock” set of fins built into the motherboard behind the CPU socket. The CPU could get attached to it with a pad or paste on the back.
- mook 3y ago
  A couple years back they noted that they were looking at having essentially cooling pipes _inside_ the chips. There hasn't been much noise in terms of commercialization, but that's the kind of extreme they were looking at. https://www.tomshardware.com/news/tsmc-exploring-on-chip-semiconductor-integrated-watercooling https://www.tomshardware.com/news/tsmc-exploring-on-chip-sem...
- dist-epoch 3y ago
  > cooling both sides of the CPU That would only double cooling capacity, and has costs - completely invalidates current motherboard designs.
- chainingsolid 3y ago
  Heres my first thought on how you might be able to do pin out on a 'sandwich a cpu between 2 heatsinks design'. 1) DRAM gets integrated with the cpu. Slight thickness increase, probably quite a bit of added width. We get a bigger area to cool, closer ram and no need for any memory pins. 2) Add power connections to the 2 cooling sides. Running power wires through the coolers shouldn't be an issue. 3) Run as many of the fastest PCIe lanes as you can out the 4 thin sides of the package. These end up handling ALL of the IO. Some downsides I can think of off the bat are cooking the ram chips and with so much density and heat not sure how well signal integrity would work out.

cubefox 3y ago

> Experts estimate CFETs to roll out commercially seven to ten years from now, but there is still a lot of work before they are ready. So the technology is still very much science fiction at this point.

deleted 3y ago
[deleted]
smolder 3y ago
No, they've been made, just not via scaled-up commercial production process.
- cubefox 3y ago
  The fact that they are predicted to be "seven to ten years" away suggests there are still many unsolved problems that are preventing scaling-up from becoming a reality.
  - smolder 3y ago
    Fair point. I think for comparison it's interesting that Intel spent most of a decade on a single process.

oldesthacker 3y ago

Interesting bit about Samsung’s secret sauce: Samsung went even smaller than Intel, showing results for 48-nm and 45-nm contacted poly pitch (CPP), compared to Intel’s 60 nm, though these were for individual devices, not complete inverters. Although there was some performance degradation in the smaller of Samsung’s two prototype CFETs, it wasn’t much, and the company’s researchers believe manufacturing process optimization will take care of it. Crucial to Samsung’s success was the ability to electrically isolate the sources and drains of the stacked pFET and nFET devices. Without adequate isolation, the device, which Samsung calls a 3D stacked FET (3DSFET), will leak current. A key step to achieving that isolation was swapping an etching step involving wet chemicals with a new kind of dry etch. That led to an 80 percent boost in the yield of good devices. Like Intel, Samsung contacted the bottom of the device from beneath the silicon to save space. However, the Korean chipmaker differed from the American one by using a single nanosheet in each of the paired devices, instead of Intel’s three. According to its researchers, increasing the number of nanosheets will enhance the CFET’s performance.

deleted 3y ago
[deleted]

KingLancelot 3y ago

[dead]

anthk 3y ago

Any EE member here? How's photonics' computing going?

drtgh 3y ago

In storage, moving away from 2D MLC and TLC NAND towards 3D TLC stacking (and horrendous higher bits) has introduced disturbances that literally shorten the memory life cycle. When a cell is read, the voltage alters the state of adjacent cells, which must be forced to be rewritten to preserve their state, thus shortening the life cycle of the disk just by reading data. they are selling us crap. From the little I understand about the problem, this would be solved by occupying more surface area to separate the tracks that run through the vertical stacks ? what would be like a 2D design surface area but with bigger complications. Although I have read papers[1] that propose adding latency in an attempt to mitigate (not solve) the problem. So now, reading this news about processors and stacking, I wonder about what inconveniences the end users are going to suffer with processors built under these techniques. Whether in computational reliability, vulnerabilities and so on. I wrote vulnerabilities (pure imagination and speculation of my own, I'm imagining a prefetch problem at the transistor level) because if it turns to be real at future I can see the manufacturer introducing a fix for randomly increase latencies or any other thing, and sending the computing power back ten years with an "oh, we didn't expect it such thing were possible when we designed it". And of course the computational reliability. is being taken care of to avoid all of this?.. if not, I leave my comment here for courts in the future. [1] [2021] doi.org/10.1145/3445814.3446733 (use sci-hub) [2] [2018] doi.org/10.1145/3224432 https://people.inf.ethz.ch/omutlu/pub/3D-NAND-flash-lifetime-early-retention-loss-and-process-variation_sigmetrics18_pomacs18-twocolumn.pdf https://people.inf.ethz.ch/omutlu/pub/3D-NAND-flash-lifetime...

FirmwareBurner 3y ago
>So now, reading this news about processors and stacking, I wonder about what inconveniences the end users are going to suffer with processors built under these techniques. Whether in computational reliability, vulnerabilities and so on. Denser logic hasn't got the same issues as dense non-volatile storage as logic doesn't need to have any persistence. It's what the likes of Micron and Samsung are good at fixing and working around when they launch and scale their Xnm processes for a specific storage technology, and what makes them better than competitors. Intel, TSMC, GloFo, etc they all can buy the latest gen EUV machines from ASML if they want, but yet TSMC is always one node ahead on logic and Micron and Samsung win at storage, because they're good at ironing out the kinks and challenges that come from shrinking down those specific designs closer and closer to sub-nm level while the others can not (so easily). If fabbing cutting edge silicone was as easy as just having the latest gen ASML machines, then ASML would just hoard the cutting edge machines for themselves and become vertically integrated in fabbing their own cutting chips as a side hustle before everyone else.

CalChris 3y ago

A minor startup isn't Intel, Samsung and TSMC but www.thruchip.com did 3d stacking 10 years ago. https://web.stanford.edu/class/ee380/Abstracts/141022-slides.pdf https://web.stanford.edu/class/ee380/Abstracts/141022-slides... https://www.theregister.com/2014/02/21/thruchip_communications_comes_up_with_alternative_to_through_silicon_vias/ https://www.theregister.com/2014/02/21/thruchip_communicatio...

baybal2 3y ago
[dead]
markhahn 3y ago
the case for inductive stacked chips is pretty compelling, if those slides are right! I wonder if you can also couple adjacent chips that way, since 2.5D is, if anything, more important than stacking...

coreyh14444 3y ago

From the Terminator fandom wiki: The CPU was modeled and designed primarily on computers in advanced 3-Dimensional programming packages, where simulated testing could be done in real time, or at increased rates. The lattice of cubes in the construction of the prototype CPU suggests a "hypercube", a cube of more than three dimensions. In computer design, hypercubes are used as a physical connection scheme that minimizes the effective communication distance (and therefore the time delay) between processors, when the logical connection scheme needed by the software that will be run on those processors cannot be known in advance. This then supports the Neural Net's ability to learn, adapt, and built new logical connection schemes.