9 ms·
Intel’s Manufacturing Roadmap from 2019 to 2029
- lachlan-sneff 7y agoWhat perplexes me is that neither Intel, AMD, IBM, or any other company, as far as I can tell, is pursuing the bootstrapping path of self-assembling nanotech. Once someone does it, every other company is going to be left several orders of magnitude in the dust, so it surprises me that no one is going for it.
- ttsda 7y agoYeah, I wonder why all these companies are investing billions on chip fabrication if they can just tell the tiny robots to build them
- lachlan-sneff 7y agoWell, you can laugh, but it's legitimate stuff. Right now, all we have is self-assembling dna structures, but there's a bootstrappable path towards "tiny robots".
- ttsda 7y agoWe have self-assembling dna structures, which we don't even fully understand and which are the result of millions of years of evolution. The steps are being made towards such tiny robots, but it's preposterous to mention them as a viable alternative to the current chip fab strategy.
- fooker 7y agoNo, gate sizes even one order of magnitude smaller is going to be infeasible for 'electron'-ics.
- lachlan-sneff 7y ago"*nm" gates is just marketing speak. The transistors are actually still many 10s to 100s of nanometers across. Actual nanotech will allow for gates that are legitimately just a few nanometers across.
- luc4sdreyer 7y agoHave you considered that self-assembling nanotech might be much, much harder than it seems? Or do you know something we don't?
- lachlan-sneff 7y agoOh no, it is extremely complex. However, every step along the path towards it provides benefits and, slowly but surely, researchers are moving forward. I think the field just needs more funding and more scientists dedicated towards it.
- luc4sdreyer 7y agoThat's fair. Deciding how much to spend on R&D and what to prioritise is a hard problem.
- bloopernova 7y agoI believe that the nanobots required to perform such a feat are at least several decades away, if not further. You're essentially trying to replicate what cells do in a growing embryo, and even with several billion years of evolution that is still a very very error-prone process.
- lachlan-sneff 7y agoYou're right about the self-replicating part, that's probably very far away (and not necessary for this). But I think self-assembling nano-mechanisms are closer. We can already sort of do it with self-assembling dna mechanisms and, theoretically, those can bootstrap into more complex tech made out of better materials
- kuu 7y agoHow is it possible to have 1.4nm transistors?
- riffraff 7y agothe "nm" doesn't mean what you think it means, since some time ago it's become unrelated to actual physical dimensions, and now it just means "a better process". EDIT: for something to read https://en.wikipedia.org/wiki/10_nanometer https://en.wikipedia.org/wiki/10_nanometer
- ossworkerrights 7y agoSo it’s marketing speak.
- 0-_-0 7y agoNot exactly, it means something like "it has the same transistor density as if we shrunk transistors from about 20 years ago to 1.4 nanometers"
- davnicwil 7y agoThis comment is the first time I've seen the why of this number explained, thanks. Like, makes sense, it must be tied to some relative scale that's vaguely comparable across companies otherwise it's just kind of silly. I obviously can understand the 'marketing speak' argument but past a certain point it becomes literally nonsense if people are just using arbitrary numbers.
- jbverschoor 7y agoNever knew.. Ok.. so instead of nm, it is used as density. Shouldn't they just be using transistors per mm2, or maybe per cubic micron? mu3? I guess it's the same as LEDs.. watts/lumen.
- 0-_-0 7y ago
- huffmsa 7y ago5 and 10 year plans are always over optimistic projections by people who can't deliver in the present to reassure investors faith. They might ship 1.4nm, but it has a good chance of having Soviet tractor quality.
- unixhero 7y agoInteresting analogy. Soviet tractors famously were slow to arrive.
- huffmsa 7y agoAnd half didn't work / only met the specifications in appearance, but not so much functionality
- jacquesm 7y agoAnd were typically indestructible once they did run. Soviet pre-fall engineering was ugly and the factories sucked but the designs were solid and could run for ever with very little maintenance.
- Dylan16807 7y agoThough CPUs are already all extremely durable. So an under-specced indestructible CPU is... just an under-specced CPU.
- perceptronas 7y agoI usually hear the opposite: people tend to underestimate what they can do in 10 years and overestimate what they can do in 1-3
- huffmsa 7y agoPeople maybe, but institutions and organizations go the other way. Human capital turnover, market trends, butterflies in Thailand all conspire to foil grand organizational visions.
- baybal2 7y agoA poorly held secret in the semi industry is that transistors have stopped scaling at around 30nm - the practical limit of 193nm litho. What has been scaling was the amount of free space in between them, metal layers, design rules, cell designs and such. Before transistor scaling stalled, any process node shrink was an automatic performance gain without any side effects, but not so much after. Some designs may well be seeing net losses with process shrinks these days. From 10nm on, higher density is actually hurting your performance, not adding it. For a process technologist, you have now to work on both performance, and density in parallel, and not solely on the last one thinking that gains in it will automatically translate into gains in performance. So its a tricky business now to both squeeze more transistors into a design, and have a net gain from it.
- josteink 7y ago> Intel expects to be on 2 year cadence with its manufacturing process node technology, starting with 10nm in 2019 and moving to 7nm EUV in 2021 Not to say it could never happen, but given how many years Intel has spent on 10nm with it always been 'next year' tech year after year, 7nm in 2021 seems overly optimistic for me. I guess time will tell if they got it right this time.
- thunderbird120 7y agoIt seems reasonably likely that they will succeed. Intel's 10nm and its 7nm are very different beasts with 7nm arguably being a lot simpler thanks to EUV and a 2x density transistor improvement goal (vs 2.7x for 10nm). The lack of EUV and very high density goals for 10nm meant they had to do a lot of multi-patterning which ended up screwing their yields. That plus the uncharted waters of using cobalt interconnects rather than copper meant it was basically Intel getting overconfident and being too ambitious for their own good.
- Symmetry 7y agoThere were also a whole laundry list of other technologies Intel was trying to put into 10nm. Contact over active gate, COAG, was heavily used in the GPU portion of the die and its failure is why none of the very few 10nm parts released in 2018 had any GPU at all.
- Nokinside 7y agoAs far as I know there is no reason to think that Intel's problems with 10nm process have effect to new processes they are developing for 7nm. Core technologies change and missing a step is something that might happen to others in the future. In fact GlobalFoundries also failed their 7LP (7nm). As a result they stopped pathfinding and research for 5 nm and 3 nm and quit the race. They are moving to more specialized chips. Fab cost for new process has grown each year for decades. Now it's something like $20 billion. Stakes grow at same time as things get more hairy and complicated 'down there'.
- nightcracker 7y agoReality: 14nm,14nm,14nm,14nm,14nm.
- huffmsa 7y agoWith a few one off demo 10nm releases here and there.
- m45t3r 7y agoI am waiting for the 10nm#.
- AgloeDreams 7y agoMeanwhile TSMC is out there shipping 10nm equivalent for a year now, including in Threadripper and Apple's AX chips. Wonder if AMD will ship a next gen TSMC fabbed product prior to 10nm Shipping en Masse.
- boatswain 7y agoTSMC's 5 nm node is on track for high volume in Q2 2020[1]. They also have the announced 6 nm which they expect most clients to transition to[2]. If Intel's 10 nm is equivalent to TSMC's 7 nm then their 6 nm should be noticeably better even before 5 nm starts shipping. [1] https://www.anandtech.com/show/15016/tsmc-5nm-on-track-for-q2-2020-hvm-will-ramp-faster-than-7nm https://www.anandtech.com/show/15016/tsmc-5nm-on-track-for-q... [2] https://www.anandtech.com/show/14290/tsmc-most-7nm-clients-will-transit-to-6nm https://www.anandtech.com/show/14290/tsmc-most-7nm-clients-w...
- eyegor 7y agoWoah there pal, you're forgetting that they spun up their 22nm process again in 2018 [1]. Intel has a lot of fab headaches right now. A reminder that 22nm debuted in 2011, and 14nm was 2014. [1] https://www.anandtech.com/show/13714/intel-adds-b365-chipset-to-lineup-the-return-of-22nm https://www.anandtech.com/show/13714/intel-adds-b365-chipset...
- rrss 7y ago
- HelloNurse 7y agoThe "backporting" doctrine clearly implies total lack of faith in process roadmaps, to the point of compromising processor designs and increasing cost and time to market to avoid committing to a millstone around the neck.
- baybal2 7y agoAdding to my previous post, a lot of people don't understand where 10nm EUV litho stands in the grand plan of thins. "If EUV doesn't make a more performant chip, what it does?" EUV is there to alleviate extreme process costs associated with multiple patterning, and process cycle time. Even if EUV tool does 1 exposure a little bit slower than quadruple patterning, it can do 4 patterning steps in one — a very huge thing in process technology. You have then lessen the amount of thermal processes performed on the device. You may have more defects, but on overall higher quality, higher performance devices in the end.
- vardump 7y ago> Even if EUV tool does 1 exposure a little bit slower than quadruple patterning, it can do 4 patterning steps in one — a very huge thing in process technology. Would that also remove some patterning constraints? Give the pattern "more freedom".
- baybal2 7y agoYes, this is another big thing about it
- andy_ppp 7y agoJust as an interesting aside does anyone have a list of weird engineering hacks used in these processes to get smaller and smaller transistor densities? There must be some very clever stuff to jam them in there and still be able to etch the lines.
- yaantc 7y agoIt's a vast and complex topic. I once stumbled on the following presentation from ARM: https://community.arm.com/developer/research/b/articles/posts/the-ics-of-2030 https://community.arm.com/developer/research/b/articles/post... The first part covers EUV, which is key to advanced nodes. Then it moves on to more futuristic and tentative techniques. But the EUV part is a nice introduction for non specialist, with pointers to dig if one is interested.
- Dylan16807 7y agoEUV is an amazing nightmare, but the etching part of the process is pretty straightforward. The difficulty is in finding materials that don't absorb it all and/or break constantly. In my mind, the really interesting tricks and hacks are all the ways they've managed to take 193nm light and etch things that are so much smaller than the wavelength.
- aklascheema 7y agoThere is this interesting talk by Jim Keller. Talks about new approaches (different transistor tech, architecture, etc) to keep moores law going for another decade or so. You should defintely check it out if have time. https://www.youtube.com/watch?v=oIG9ztQw2Gc https://www.youtube.com/watch?v=oIG9ztQw2Gc
- deepnotderp 7y agoScaling boosters: https://en.wikichip.org/wiki/scaling_booster https://en.wikichip.org/wiki/scaling_booster
- sl-1 7y agoBest resource I have run in to about this is this talk: https://www.youtube.com/watch?v=NGFhc8R_uO4 https://www.youtube.com/watch?v=NGFhc8R_uO4 It quickly introduces the various hacks we do in order to get ~30nm features on silicon. But the talk is quite dated (early 2010's), but never ceases to amaze me. Semiconductors are indistinguishable from magic indeed.
- diegoperini 7y agoWhat kind material science improvement would make non-marketing, real ~10nm scales a reality? I literally have no idea how RnD works in this field. Is it trial and error? How do these scientists come up with ideas that increases the transistor density? Do our current gen CPUs have 2d or 3d curcuit layout? How one can learn about these stuff without working in the field?
- rusticpenn 7y agoThe biggest bottleneck is the laser (physics) used for etching of the layers ( and at some point, the number of electrons passing throught the gate, which intel solved using a "3D" gate.)
- kristofferR 7y agoThis is a great watch about how EUV works: https://www.youtube.com/watch?v=f0gMdGrVteI https://www.youtube.com/watch?v=f0gMdGrVteI
- diegoperini 7y agoWatched it, thanks a lot!
- marcosdumay 7y agoA less than 10nm transistor with the same design transistors had 20 years ago does basically not work (you can do some analog hackery, but it's does not behave like a transistor). Every semiconductor has a lower limit, for silicon it's ~10nm.
- brennanpeterson 7y agoGo through the lithoguru class notes on YouTube to learn. Some stuff. There are some nice talks from Kellin Kuhn or Dick James that have good detail. If.you are visual, Coventor has some nice visualizations. And I really like the work from Nikonov and Young. If you really.want to get into the ideas, the series.of.papers and notes on E-tau scaling rules are great. Maybe not complete, but good. Ideas for density aren't too hard: shrink pitch and fold into the z dimension. 3DNand is a folded NAND string, after all. On materials, it really is driven by etch and lithography (collectively, patterning). Mostly not materials themselves.
- wadkar 7y agoI really liked the last quote: > It’s worth also pointing out, based on the title of this slide, that Intel still believes in Moore’s Law. > Just don’t ask how much it’ll cost. I once got an opportunity to ask something similar to an Apple executive during a presentation on their hardware capabilities (it was a university event). He laughed and answered another part of my question.
- Shorel 7y agoMoore's Law is about cost per transistor, so they have it wrong somewhere.
- twic 7y agoMaybe they'll start charging for the resistors.
- boatswain 7y agoMoore's law is about density of transistors.
- lorenzhs 7y agoThat's not quite correct. It's about the number of transistors per integrated circuit that minimises per-transistor cost. From the actual 1965 paper: > "The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (see graph on next page). Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000." There's also the 1975 speech where he revised it down from a yearly doubling to once every two years.
- anonuser123456 7y agoThis is pretty well known in the semi-conductor industry. Everyone believes 5-7nm is the cost wall for just about everyone but Apple or Intel. Some companies are actually going the opposite direction or re-spinning new chips on older processes because of cost.
- HocusLocus 7y agoMeasure with micrometer. Mark with chalk. Cut with an axe.
- soygul 7y agoI know that past performance does not indicate future results but looking at their 2013-2016 roadmap [1] which promises 10nm at Q1 2016 (which never happened!), I strongly doubt their future roadmap will hold. [1] https://wccftech.com/intel-processor-roadmap-leaked-10nm-cannonlake-skylakee-arrives-q3-2016-skylake-muy-chips-q4-2015/ https://wccftech.com/intel-processor-roadmap-leaked-10nm-can...
- bryanlarsen 7y agoAnd for the previous 40 years Intel was always about 1 year ahead of their competitors. I would never bet against Intel, that's been a losing game for far too long.
- hrktb 7y agoAMD was already poised to eat their lunch last time, Intel had to go to illegal lengths to keep their commercial lead. I'd expect AMD to have learned the lesson and get away with their lead this time.
- seanmcdirmid 7y agoIrrelevant. AMD doesn’t own its own fabs anymore, and I think they rely on the expertise for whoever happens to be fanning their chips, allowing them to simply choose the fab with the best process while they focus on architecture.
- undersuit 7y agoMaybe that's the lesson AMD learned?
- seanmcdirmid 7y agoNo. It’s just the reality of the situation. Perhaps intel would do better to separate their fab and architecture divisions, or maybe they are already sufficiently separated internally anyways.
- eyegor 7y agoSo if Intel actually stayed on track for this roadmap, they're saying "we only have 10 years left to advance our fabs". Unless 1.4nm is actually meaningless, they'd be edging up to electron tunneling issues with a contacted gate pitch of ~10 atoms across. I'm being optimistic with this guesswork. Intel's historical naming is that cpp = 3-5x node name [1]. Silicon lattice spacing is ~0.54nm. [1] https://en.wikichip.org/wiki/intel/process https://en.wikichip.org/wiki/intel/process
- Darvon 7y agoThat was my first thought as well: "I thought tunneling made this impossible"
- staticassertion 7y agoWhat's next? Moving away from silicon? I've always heard of Graphene as the next step but I know nothing about this stuff.
- gsnedders 7y ago> "we only have 10 years left to advance our fabs" Well, only 10 years left to advance with silicon wafers; once improvement truly becomes impossible there presumably we'll see even more resources go into trying to find practical replacements.
- PedroBatista 7y agoYou can always count on Intel's marketing team for top notch slide presentations. However, Intel is closer to 22nm than 7nm let alone anything smaller than that. ( I'm talking about consistent product lines that anyone can buy at a store ), not some Houdini show. On the commercial side they have a huge footing and large tentacles so they don't need to worry too much about time-frames, let's hope they also don't worry too little..
- metalforever 7y agoSounds like bullshit.
- deleted 7y ago[deleted]
- nootropicat 7y agoFor comparison, Intel's roadmap from IDF2013: https://files.catbox.moe/psgnbp.jpg https://files.catbox.moe/psgnbp.jpg
- RosanaAnaDana 7y agoSo, long AMD? Edit: oof with the down votes. Jesus people; comma added for clarity.
- fooker 7y agoNice one
- bullen 7y agoAll change requires energy, and we're going to have less energy, so the speed of change inevitably has to go down. Because the only energy added to the planet comes from the sun and the only viable option to collect that energy are trees and plants. (I'm going to post this comment on every naive technology optimist post, you can downvote me all you want, I have to do this to be able to sleep at night, fake karma is not more valuable than real karma)
- randyrand 7y agoI've read that as chips get smaller, their working life gets shorter. Anyone have more info?
- opwieurposiu 7y agoI think you are talking about Electromigration https://en.wikipedia.org/wiki/Electromigration https://en.wikipedia.org/wiki/Electromigration
- dmos62 7y agoA beginner question: what's the motivation behind reducing chip size? Less power consumption?
- Rebelgecko 7y agoLess power consumption and/or the ability to cram more transistors into the same area. Less power consumption also means less heat generated. I think heat dissipation is the main roadblock to faster CPUs (faster in terms of clock speed). IANAEE but I think the speed of light becomes a big issue at higher clock speeds. Putting transistors physically closer to each other helps reduce problems with propagation delay.
- dmos62 7y agoLately, I've been asking these "simple" question more often on HN. They are consistently down-voted: I can't imagine why.
- marcosdumay 7y agoSmaller transistors bring everything. They have lower resistance and capacitance resisting a switch, you can build more of them at the same time (so, approximately by the same cost), a signal takes less time to pass through them (and to get from one to another), and they have a larger surface/volume ratio for cooling down. That said, transistors actually stopped shrinking a while ago. They are getting packaged nearer to each other, they have changed from horizontal to vertical, and they are changing the width/length ratio, but they are not really shrinking.