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Darpa invests $100M in a silicon compiler
- deleted 8y ago[deleted]
- eleitl 8y agoThought I'll see Olofsson in there.
- archgoon 8y agoSounds like you're familiar with this space and this guy; any thoughts you'd like to share?
- ingenieroariel 8y agoI'll bite but consider all I write poorly informed wild speculation. The person he mentions has been behind a lot of advancements in both getting cheap FPGA based boards to the hands of users and creating libre silicon-proven IP. He recently left his company that was making Zedboards and Parallella among other things to join DARPA. The last big project he seemed to have worked on was a 1000-core processor of which a lot was open source but a lot of the important bits were protected due to likely an NDA with the factory or the provided of the tools they used. It hope what he is going to work on (EDA) will finally enable DARPA and others to fund truly open source designs and tools and work with fabrics that would allows access to really cheap ASICs or FPGA based systems, building on all the momentum around platforms like RISCV and his experience creating the Epiphany cores.
- ingenieroariel 8y agoOH! is an open-source library of hardware building blocks based on silicon proven design practices at 0.35um to 28nm. The library is being used by Adapteva in designing its next generation ASIC. https://github.com/parallella/oh https://github.com/parallella/oh
- mips_avatar 8y agoI wish FPGA design tools just worked...
- robotresearcher 8y agohttps://www.darpa.mil/staff/mr-andreas-olofsson https://www.darpa.mil/staff/mr-andreas-olofsson
- JumpCrisscross 8y agoSide note: when people complain about the military budget, projects like these should be noted. Political reality in America, today, is military R&D and jobs programs are easier to fund than civilian ones; so that’s where projects go to live.
- mmiller9 8y agoI sincerely doubt our enormously bloated defense budget is because of research...
- killjoywashere 8y agoThe DoD budget exceeds Google's market cap, and their research budget exceeds Google's annual revenue.
- ProAm 8y agoBut they dont spend it nearly as efficiently. Gov is slow and bloated. It's why government contracts are so coveted, lots of money, long term contracts, overages are just part of life.
- deleted 8y ago[deleted]
- mips_avatar 8y agoOk but if 200 planes need to be upgraded so that they don't get shot down by ____ new weapon. It's not possible to build an ASIC for this, so you're probably looking at doing something on an FPGA. You need a few FPGA hardware engineers, electrical engineers, software engineers. Even if the project only takes a year to design, build, and test. And then you spend an extra 6 months because xilinx's fpga tools basically don't work. You've got minimum $1 million dollars in salary, and that's not including the facility, materials, and testing costs. Even if the program costs $20 million, if it saves 40 planes, you can't tell a dead airmen's family that their loved ones life wasn't worth $500,000.
- adrianmonk 8y agoSo it costs $500 million every time someone designs a SoC and (before now) nobody has spent $100 million trying to make that more efficient?
- darzu 8y agoThey have. The problem is that efficient silicon layout is NP-complete and automated tools can't do better than humans today. At best they can assist and detect certain classes of errors. I'm sure Intel has invested more than $100 million on tooling by now.
- ur-whale 8y agoThere are many NP complete problems where computer do vastly better than humans. But when it comes to EDA, the utterly closed-source culture of the industry has completely prevented what essentially amounts to a horde of smart people to work on the problem: no one - except a very small number insiders - even know what the problems are.
- detuur 8y agoYou couldn't be any more dead-on. EDA feels like Scientology, where with every level closer to the core you first need to invest half your life savings + a firstborn. I have an FPGA lying on my desk I can do barely anything interesting with because there are no open-source cores for even simple things like USB3.1 controllers or Thunderbolt or pretty much any interesting bus. Protocols are strongly guarded open secrets where everyone in the industry knows how they work (like MIPI for example) but God Forbid anyone outside the industry might show interest in them. Then you first need a $100k annual membership to the foundation and need to sign and NDA with your blood and that of the next three kin in line. There's a cargo cult confidentiality that achieves absolutely nothing if not completely frustrating out anyone who tries their best to keep their interest in it alive.
- gascan 8y agobecause there are no open-source cores for even simple things like USB3.1 controllers or Thunderbolt Those are hardly that simple. There exist entire companies whose function is designing such cores (and licensing them).
- ur-whale 8y ago"Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … " This, to the 100th power. The culture in the EDA industry is stuck in the 1950's when it comes to collaboration and sharing, it's very frustrating for newcomers and people who want to learn the trade. As was pointed out by someone in another hardware related HN thread, what can you expect from an industry that is still stuck calling a component "Intellectual Property"? The un-sharing is built into the very names used to describe things.
- sametmax 8y agoThey have been some attempt. E.g: the mit project called sirus that used python 2.5 as a dsl to describe high level components you could combine and reuse and then process to generate system c or verilog. Unfortunaly, while the tool is pretty nice, it never resulted in major adoption (qualcom has some tool using it internally and a few others) and we haven't seen the idea of making reusable libs and components florish. Somebody would need to find this project and up it to python 3.6. With current tooling, it would make writting code in it really nice and ease the creation of reusable components. Reusability in raw verilig is hard
- rixrax 8y ago>> "Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … " I'll have popcorn ready for the eventuality where IP blocks are widely available under GPL type of FOSS licenses and Intel|AMD|ARM|TI|... is eventually found to include one or more of those open sourced blocks with incompatible license in their chips.
- dalbasal 8y agoI have questions, if anyone knows something about hardware. What would a "silicon compiler" let one do? What exactly gets easier/cheaper and what exactly could new chip designs yield?
- gmueckl 8y agoI only have a vague idea aboutthe first two of your questions: I guess they use the term silicon compiler as a description of an ideal state in chip synthesis software where you can go from high level logic descriptions (VHDL source) to the final chip masks without any human intervention. Right now, this requires a lot of manual work in intermediate stages of the process. Being able to do away with that would simplify and speed up the process. But this also means tackling pretty nasty NP complete optimization problems.
- hardwarefriend 8y agoIt's difficult for me to be sure, since the article makes it sound as if they're attempting something novel, but synthesis tools are standard in ASIC/FPGA design flows. Currently, the best synthesis tools are closed-source and extremely expensive. Imagine the benefit of having gcc/clang be free software. That is the kind of effect that is at stake here. Usually, hardware designers will write RTL code (Verilog/VHDL) which describes the hardware slightly above the gate level. In order to turn this description into a web of logic gates (called a netlist), the design is processed by a synthesizing program. The produced netlist describes exactly how many AND, NAND, OR, etc. gates are used and how they're connected, but it doesn't actually describe where the gates are placed on the chip or the route the interconnections take to connect the gates. To generate that info, the netlist is fed into another synthesis tool (usually called place and route). This is a simplified version, but even at this level of detail, there are important factors affecting chips. - How many gates? (less might be better) - How far are the gates from each other? (closer is better; less power, area, cost, timing) - How often will the gates switch? (less is better) - More.... More advanced synthesis tools improve area, cost, power, timing. They also allow designers to have less expertise and still obtain the same result as experienced designers by optimizing out micro-level inefficiencies in the design (though experienced designers will also lean on the synthesis tool).
- alexbeloi 8y agoA great blog post here (https://wp.josh.com/2017/10/23/adventures-in-autorouting/ https://wp.josh.com/2017/10/23/adventures-in-autorouting/) about some different auto-routing software.
- arbie 8y agoOne of the main points the post is missing is the distinction between a placer and a router. Most (all?) PCB design tools do not come with a connectivity-based placer. They only ship with a maze-, grid- or shape-based router. Placement and Routing together is generally the domain of the very-expensive EDA tools inferred in the main article.
- analognoise 8y agoThose routes look terrible. Maybe if everything you're doing is electrically short and there are no high speed routes, it would work great. Basically it's wonderful if all you make are blinkenlight projects. But if you have to input all of the data that makes up a good route (including coupling, ground/power planes, trace length matching, PDN noise, stackup, EMI/C rules, etc, etc), and then review the whole thing anyway, what's the point of the autorouter? Also the article says nothing about the various algorithms involved, which are interesting from a computational geometry standpoint. But the gulf between algorithm or academic example and "commercial router" is huge! This blog post is just... not very good. It's how I imagine a software person who made some stupid blinky LED thing thinks about hardware.
- petra 8y agoI see many chip vendors on the list of participating companies. Won't this project reduce barriers to entry for their industry ? and if so, isn't it against their interests to participate?
- ekroa 8y agoI don't buy it. Having Cadence and Synopsys involved it is like DARPA invites Mathworks to do an open-source version of Matlab.
- ur-whale 8y agoI don't believe keeping barrier of entry high in an industry is a good thing for companies in that industry. Quite the contrary, lowering barriers creates more opportunities and thereby new scope for growth. It took MSFT 30 years to finally understand that lesson and start offering a free suite of dev tools. The EDA industry still hasn't groked that lesson.
- nickpsecurity 8y agoMicrosoft knew what they were doing: using secrecy, obfuscated formats/protocols, copyright law, and patent law to block as much competition as possible. They made billions in the process. The EDA vendors do something similar but mostly acquire competitors. There's just three of them covering the basics parts of ASIC design. They aren't competing on driving prices down, either. So, their strategy is smart until they, like Microsoft, get in a situation where less and less customers need them. I did think one could do a more open version of EDA, though. I was gonna try to talk to someone at smaller player, Mentor, but they got bought. Im keeping my eyes open for new players wanting a differentiator.
- TomVDB 8y agoThe participating companies makes chips that requires a huge amount of resources to make them happen: design engineering time, CAD software, tape-out cost, validation engineering time, ... The CAD software is expensive, but it's not barrier of entry expensive compared to design engineering time, tape-out cost etc. If the CAD software cost gets reduced, it would result in a cost reduction of all companies involved while still having a barrier of entries that's be way too high for anyone but the best funded companies.
- wcrichton 8y agoMy advisor at Stanford is working on an open-source hardware toolchain to solve these exact problems. The Agile Hardware Center is trying to bring software methodologies of rapid prototyping and pervasive code sharing/reuse to ASICs, CGRAs, and FPGAs: https://aha.stanford.edu/ https://aha.stanford.edu/
- mips_avatar 8y agoAny tips on getting started with FPGA on custom pcbs?
- phendrenad2 8y agoPower requirements are annoying. You need multiple voltages and they need to ramp up in a certain sequence at a certain ramp rate(!). Study reference designs - find a development board that has the same family of FPGA and also has published schematics and board layout (such as Intel and Xilinx official boards). Then just copy their power layout.
- civilitty 8y agoWhat exactly do you mean by "getting started with FPGA on custom PCBs?" Have you made custom PCBs with high density BGAs before? Most non-trivial FPGAs (to me that means you can easily fit a decent softcore processor with space left over for your FPGA logic) will be ball grid arrays and almost impossible to DIY without xray inspection equipment and a reflow oven. You can get what you need for a few hundred $ on eBay if you're patient and lucky but even then, getting to the point where you can solder the chips reliably will take time. If you have the budget for professional assembly, then I would start with a Digilent product that has an available reference design you can copy later. First get used to the FPGA and how it works (they are largely incomparable to a CPU or GPU except for the fact that they both have transistors). Then, design a simpler board with a smaller FPGA and work your way up to the big 500-1k pin chips.
- specialist 8y agoAside: Have you ever considered a DIY youtube channel? If you, @slededit, others on this thread did something like Louis Rossmann, that'd be fantastic. I've never even seen a dentist's x-ray machine, much less seen it used for DIY design. That'd be amazing to watch. Louis Rossmann https://www.youtube.com/channel/UCl2mFZoRqjw_ELax4Yisf6w https://www.youtube.com/channel/UCl2mFZoRqjw_ELax4Yisf6w (But maybe y'all would dial down the rhetoric from an 11 to a 8 or 9.)
- baybal2 8y agoI don't see how this is not literally the same thing any HDL synthesis program does. How?
- ThinkBeat 8y agoI don't quite get the open source angle in the comments here. If I managed to get my grubby hands on a moderately modern computer, I can use all manner of open source software and I can create wonderful new software. The barrier of entry is fairly low in rich countries. If AMD open sourced all the design aspects of their chips, I would have to get a loan to build 100 million fab to have any practical manner to enjoy it? I can see that if Intel/AMD/NVidia/Apple shared all aspects fo their chips cross pollination might bring great things, and academic research would be boosted and might end up giving back more to the community at large, but you are talking about very few entities across the world that can afford fabs.
- civilitty 8y ago> If AMD open sourced all the design aspects of their chips, I would have to get a loan to build 100 million fab to have any practical manner to enjoy it? Try $1 to 5 billion. We're talking about something that over half of all extant nation states wouldn't be able to pull off without devoting 10-50% of their annual GDP to the project.
- solarkraft 8y agoEven the large designers (AMD, Apple, Mediatek) don't have their own fabs. You would "just" need to order a design made - probably for hundreds of thousands of chips to make any sense. Is there information on what this step would actually require?
- civilitty 8y agoFirst, you have to choose your feature size and manufacturer based on your specs because that will lock down your available cell library. Cell libraries are an abstraction over the masks/dopants and describe how to fab the transistors and higher level logic gates, made by each manufacturer for each feature size. STM, TSMC, Global Foundries, etc. have their own cell libraries and each process node gets a different one (there could also be different libraries for consumer, medical, automotive, etc.). If your design isn't pushing the physical limits of your chosen process, you can usually use a standard cell library supported by your synthesizer so that you can stay in HDLs instead of tweaking masks. Once you've finished your design (I'll leave this as an exercise to the reader :)), you'll start a back and forth with the foundry which will run its own database of rules against your design and work with you to make tweaks that better fit their fab. After you agree on a final mask, you and the fab will run verification simulations and eventually, after several months, you'll get your chips with that new factory smell. Yes, you can "just" order some chips made. I don't have the URLs off the top of my head but there are a few companies here in California that I've worked with. You can literally walk into their offices unannounced and if you have the money, they will start right then and there. If I remember correctly, in 2012 it cost about $100k to get started with STM's 45nm process (might have been 28nm by then, don't remember). Today, 28nm can cost as low as $4-12k if you're a Canadian researcher [1] - although that's almost certainly subsidized. It all seems scary only because the process is so complex that no one person has a grasp on even a minor fraction of what's going on. [1] https://www.cmc.ca/en/WhatWeOffer/Products/CMC-00200-02843.aspx https://www.cmc.ca/en/WhatWeOffer/Products/CMC-00200-02843.a...
- kenferry 8y agoThis kind of spending is so foreign to me. At $250,000 per year per person, that supports 100 people for four years. I… suppose that's not completely insane?
- garmaine 8y agoFully loaded (inclusive of benefits, payroll tax, etc.). That’s actually not a lot.
- deleted 8y ago[deleted]
- Aeolus98 8y agoI might be able to weigh in here. Having these tools as open source and freely available is a huge deal for so many industries. I've worked with these tools at an academic level and now at a startup, and it's amazing the magnitude of this enabling technology. Just the tooling investment will be huge, making the core solvers and algorithms more accessible should spawn a whole new wave of startups/research in effectivley employing them. Just these days, I've heard of my friends building theorem provers for EVM bytecode to formally check smart contracts to eliminate bugs like these [0]. These synthesis tools roughly break down like this: 1. Specify your "program" - In EDA tools, your program is specified in Verilog/VHDL and turns into a netlist, the actual wiring of the gates together. - In 3D printers, your "program" is the CAD model, which can be represented as a series of piecewise triple integrals - In some robots, your program is the set of goals you'd like to accomplish In this stage, it's representation and user friendliness that is king. CAD programs make intuitive sense, and have the expressive power to be able to describe almost anything. Industrial tools will leverage this high-level representation for a variety of uses, like in the CAD of an airplane, checking if maintenance techs can physically reach every screw, or in EDA providing enough information for simulation of the chip or high-level compilation (Chisel) 2. Restructure things until you get to a an NP-complete problem, ideally in the form "Minimize cost subject to some constraints". The result of this optimization can be used to construct a valid program in a lower-level language. - In EDA, this problem looks like "minimize the silicon die area used and layers used and power used subject to the timing requirements of the original Verilog", where the low level representation is the physical realization of the chip - In 3D printers it's something like "minimize time spent printing subject to it being possible to print with the desired infill". Support generation and other things can be rolled in to this to make it possible to print. Here, fun pieces of software in this field of optimization are used; Things like Clasp for Answer Set Programming, Gurobi/CPLEX for Mixed Integer programming or Linear programs, SMT/SAT solvers like Z3 or CVC4 for formal logic proving. A lot of engineering work goes into these solvers, with domain specific extensions driving a lot of progress[1]. We owe a substantial debt to the researchers and industries that have developed solving strategies for these problems, it makes up a significant amount of why we can have nice things, from what frequencies your phone uses [2], to how the NBA decides to schedule basketball games. This is the stuff that really helps to have as public knowledge. The solvers at their base are quite good, but seeding them with the right domain-specific heuristics makes so many classes of real-world problems solvable. 3. Extract your solution and generate code - I'm not sure what this looks like in EDA, my rough guess is a physical layout or mask set with the proper fuckyness to account for the strange effects at that small of a scale. - For 3D printers, this is the emitted G-code - For robots, it's a full motion plan that results in all goals being completed in an efficient manner. [0] https://hackernoon.com/what-caused-the-latest-100-million-ethereum-bug-and-a-detection-tool-for-similar-bugs-7b80f8ab7279?gi=e1d1a15e098a https://hackernoon.com/what-caused-the-latest-100-million-et... [1] https://slideplayer.com/slide/11885400/ https://slideplayer.com/slide/11885400/ [2] https://www.youtube.com/watch?v=Xz-jNQnToA0&t=1s https://www.youtube.com/watch?v=Xz-jNQnToA0&t=1s
- cottonseed 8y agoThey should have given 1% of it to Clifford Wolf.
- slededit 8y agoIt should be noted that Andreas Olofsson used to run Adapteva and close to singlehandedly designed the Parallella processor.
- tlrobinson 8y agoI wonder if the decline of Moore’s Law will eventually lead to the commotidization of ASIC fabrication? Of course fabricating a chip will never be as cheap as writing a bit of software, but maybe it will eventually be as cheap as, say, injection molding a piece of plastic?
- Aeolus98 8y agoNo matter what, you'll need to clear a certain volume floor. Masks are expensive [0] especially for nicer process nodes. Once you have a mask set and fab time, it's off to the races. IMO $1M really isn't bad for a simple chip run. [0] https://anysilicon.com/semiconductor-wafer-mask-costs/ https://anysilicon.com/semiconductor-wafer-mask-costs/
- StringyBob 8y agoHeading the opposite direction - at least for the bleeding edge 7nm/5nm/3nm ASICs you want in your next computer or smartphone. Manufacturing costs (particularly fixed costs) are going up exponentially. We're getting stuck on economics before physics. You need to be able to sell 10million+ parts to cover your costs. There's more opportunities if you don't need the best performance or lowest power and use an older manufacturing process node like 65nm.
- spencerg12 8y agonice
- 437598735 8y agoOn the opposite side of the spectrum, there's Chuck Moore (Forth creator) who in trying to find the simplest combination of software and hardware for his projects devoted a lot of time into a DIY VLSI CAD system. Fascinating history behind it, although the actual OKAD system is essentially trade secret for his company. His site has been down for a while, but someone thankfully mirrored most of the pages here: https://colorforth.github.io/vlsi.html https://colorforth.github.io/vlsi.html More history about OKAD, plus links to more about Forth both software and hardware: http://www.ultratechnology.com/okad.htm http://www.ultratechnology.com/okad.htm
- zik 8y agoI'm surprised to see no recognition of yosys, arachne-pnr and the icestorm tools which together are a free and open source HDL tool chain which already exists and is pretty widely used.
- ur-whale 8y agoThese two projects are exactly the road the EDA industry should be taking. Unfortunately, they make very slow progress because they have to painstakingly reverse-engineer everything (with the possible exception of Lattice stuff). For Xilinx chips, where exactly nothing is publicly documented at the lower levels of the stack, they have to spend mountains of time re-discovering everything. Even if I deeply admire the effort and how far they've gotten, I can't help but think: what a terrible waste of human talent and time. Edit: I once asked a Xilinx employee why they didn't OpenSource their entire software stack, because it struck me that they were in the chip manufacturing business, and not in the toolchain business (a blisteringly obvious fact when you look at the quality of such monstrosities as, e.g., Vivado), and that OpenSourcing the tools would potentially enlarge their potential target market by a large margin. The culture is so broken in that space that I don't think he even actually understood the question.
- cottonseed 8y ago> with the possible exception of Lattice stuff > For Xilinx chips, where exactly nothing is publicly documented at the lower levels of the stack, they have to spend mountains of time re-discovering everything. The situation with Lattice parts was the same; they reverse engineered them.
- ur-whale 8y agoThanks, didn't realize that, in my naiveté I thought Lattice actully helped :(
- 437598735 8y agoNote I don't work at Xilinx. And be prepared that what I'm about to write may seem incredibly cynical, sorry. But if I were to take a guess at why the culture is the way it is, I'd say that it's because programmable logic is fundamentally relatively small logic tiles replicated across large areas. That means across competing companies there's a high chance for infringing upon arsenals of patents for rather mundane things like interconnect, logic families, or memory cell layout where there are only a handful of viable alternatives yet the patent offices were likely duped into accepting multiple legalese interpretations of the same underlying tech. It's a minefield. Xilinx is not really a chip manufacturing business either. They're fabless. Imagine having a company that designs RAM memory and outsources everything beyond the cell design. If you don't own the foundry itself you're not going to last very long unless you encrypt the memory access protocols, obfuscate your (probably patent infringing) hardware architecture by layers of undocumented tooling, and dominate the industry by buying up any upcoming contenders while cross-licensing stuff to build up a complex ecosystem of interdependent tools required to get even the most basic project done.
- Havoc 8y agoI thought chips are already largely algo designed?
- esmi 8y agoWhat even is this project? There are no details on the DARPA page either. Is it for PCB design, ASIC design or both? Is a constant current source also considered a “small chip” or just digital designs? Basically every EDA tool already has the ability to group sub modules which one could distribute as open source if they chose. Do it in kicad and put your circuit into a hierarchal symbol if you must be all open source. I get hard IP blocks from vendors all the time for inclusion in our ASICs. It’s not the EDA tools that are preventing “openness”. I was just joking the other day how all the PCB designs I’m reviewing lately are just conglomerations of app note circuits and it’s really boring. So to me it seems like there’s plenty of design reuse. :)
- absurdmind 8y agoIt would be great if they could make something like a Bluespec Verilog[0], but open source. This HDL is far better than traditional ones, IMHO. [0] https://en.m.wikipedia.org/wiki/Bluespec https://en.m.wikipedia.org/wiki/Bluespec
- whaaswijk 8y agoI just got back from the Design Automation Conference in San Francisco. It is one of the major EDA conferences. Andreas Olofsson gave a talk about the silicon compiler. There was serious discussion about open source EDA. As far as I could tell it is still unclear what the role of academia will be. It seems tricky to align academic incentives with the implementation, and most importantly, maintenance of an open source EDA stack. However, there is quite some buzz and people are enthused. A first workshop, the "Workshop on Open-Source EDA Technology" (WOSET) has been organized. I also thought I'd try to answer some questions that I've seen in the comments. Disclaimer: as a lowly PhD student I am only privy to some information. I'm answering to the best of my knowledge. 1) As mentioned by hardwarefriend, synthesis tools are standard in ASIC/FPGA design flows. However, chip design currently often still takes a lot of manual work and/or stitching together of tools. The main goal of the compiler is to create a push-button solution. Designing a new chip should be as simple as cloning a design from GitHub and calling "make" on the silicon compiler. 2) Related to (1). The focus is on automation rather than performance. We are okay with sacrificing performance as long as compiler users don't have to deal with individual build steps. 3) There should be support for both digital, analog, and mixed-signal designs. 4) Rest assured that people are aware of yosys and related tools. In fact, Clifford was present at the event :-) Other (academic) open source EDA tools include the ABC for logic synthesis & verification, the EPFL logic synthesis libraries (disclaimer: co-author), and Rsyn for physicial design. There are many others, I'm certainly not familiar with all of them. Compiling a library of available open source tools is part of the project. Edit: to be clear, WOSET has been planned, but will be held in November. Submissions are open until August 15.
- cottonseed 8y ago> Compiling a library of available open source tools is part of the project. Compiling? What's that even mean? What about funding? I wrote arachne-pnr, the place and route tool for the icestorm stack. My situation changed, I didn't see a way to fund myself to work on it and I didn't have the time to work on it in my spare time. I assume that's one of the reasons Clifford is planning to use VPR going forward (that, and it is almost certainly more mature, has institutional support at Toronto, etc.) I would have loved to work on EDA tools. I've moved on to other things, but I wonder if these programs will fund the likes of Yosys/SymbiFlow/icestorm/arachne-pnr.