gsmecher

9 ms·

31.
by gsmecher 4y ago
I don't think this is true - on Xilinx, you can coax a DSP48 macro into implementing a barrel shifter, but the underlying primitive is a multiplier and not a barrel shifter. Unlike adders, a barrel shifter does not generalize well enou
32.
by gsmecher 4y ago
I've heard of the ZPU in passing but never looked in much detail - I didn't realize there was a GCC back-end for these machines. James Bowman's J1 CPU [0] is also stack-based and has definitely helped me shape my preferences.
33.
by gsmecher 4y ago
Yup! Thanks for pointing OPC [0] out. These CPUs were a huge eye-opener - and a huge lesson about the value of using a standardized instruction set. Building a custom CPU commits you to writing an assembler and listing generator - which is
34.
by gsmecher 4y ago
What you see is all there is. At a certain scale, it's conventional for hardware designs to become complex enough that it's necessary to structure them in hierarchies, just to maintain control. This design is small enough that non
35.
by gsmecher 4y ago
Understood. Maybe this landed after your project - but both PicoRV32 and SERV now support compressed extensions, at some additional resource cost. FemtoRV32 Quark doesn't - which is not a knock, since it's a beautifully simple imp
36.
by gsmecher 4y ago
PicoRV32 and FemtoRV32 are both excellent, conventional RISC-V implementations, and are more complete and proven than Minimax. Relative to the size of any 7-series or newer Xilinx FPGA, the difference in LUT cost between any of the three is
37.
by gsmecher 4y ago
I don't think the RISC-V spec cares, either, since it specifies an execution environment but not interfaces. A narrower data bus would allow a 2-cycle execution path, and would likely split the longest combinatorial path in the current
38.
by gsmecher 4y ago
This core is targeted at "smaller-is-better" applications with few actual instruction-throughput requirements. If it reaches 200 MHz on a Xilinx KU060, I will be delighted. (That specific clock frequency on that specific part carr
39.
Show HN: Minimax – A Compressed-First, Microcoded RISC-V CPU(github.com)
171 points by gsmecher 4y ago|38 comments
40.
by gsmecher 4y ago
The author has two beefs: 1. Clearly, he's upset about inappropriate treatment of Ukrainian citizens. (Fine - so am I.) 2. He's also upset at being forced to use Azure IoT frameworks when most FPGA applications don't need (or
41.
by gsmecher 5y ago
I design instrumentation for telescopes, in which C code on an embedded processor peeks and pokes device registers on an nearby FPGA. This C code forms an interface between hardware and the network. In this system, I write a given function
42.
by gsmecher 5y ago
I was specifically commenting on cpp-style macros. Apologies if this was unclear.
43.
by gsmecher 5y ago
To date, C's most proximate (management-friendly, technically similar, programmer-skill-adjacent) competition has been c++. (I'm trying to lay the groundwork for the next statement: I'm not claiming this is good, and excited
44.
by gsmecher 5y ago
You're absolutely correct, boost::preprocessor has an obligation towards backwards compatibility that independent efforts do not. This obligation is a double-edged sword: when I pick a library, I want it to be modern; 5 years later, I
45.
by gsmecher 5y ago
There are good reasons to reach for macro libraries. They're rare, but they're out there. I make heavy use of boost::preprocessor in a C project and it was fundamentally enabling. I have occasionally cursed at it but never regrett
46.
by gsmecher 5y ago
This is a good time to mention a Python experiment [1] that "covers up" Python 3.x's coloured asyncio with a synchronous wrapper that makes it more user-friendly. It's been posted here before [2]. I've pushed ahead
47.
by gsmecher 6y ago
We use YAML to capture a structured description of a large instrument deployment. Comments are absolutely key for us. The YAML is revision controlled in git and annotating it as a document (rather than as data) is a huge benefit. Tagged YAM
48.
by gsmecher 6y ago
YAML has such a comic-book reputation around here that I want to offer a defense of it. Many criticisms of YAML are either about adding non-YAML bits (like turing-complete templates) on top of it, or complaining that it's a bad JSON su
49.
by gsmecher 6y ago
I return to this essay about once a year, when I hear the siren-song of minimalism and am tempted to implement a Forth CPU. It's situated exactly in the no-mans'-land between FORTH and "C" camps and effortlessly slides b
50.
by gsmecher 6y ago
AsciiDoc (the format) is currently being developed in an Eclipse Foundation working group ( https://projects.eclipse.org/working-group/asciidoc ). This working group includes leads from both the Asciidoctor/Ruby a
51.
by gsmecher 6y ago
Neither Xilinx nor Intel are in the business of making simulators (and in both cases, it shows). If there is an opportunity to graft the LLVM model into the FPGA world, IMO it's the simulators. Unfortunately it requires some creativity
52.
by gsmecher 6y ago
Tooling tends to stack vertically in software: you can put together Jython-on-JVM-in-Docker-on-Linux-in-EC2 if you want to, without every layer diminishing the ones above and below it. In EDA, tooling stacks horizontally. At minimum, I need
53.
by gsmecher 6y ago
The economics of FPGAs and ASICs over the past few decades are covered really well in [1]. It's almost always about production volume. The FPGA's ability to be reprogrammed is often a convenient side-effect. In short, no, this doe
54.
by gsmecher 7y ago
Thanks, OSTree sounds like a good place to start.
55.
by gsmecher 7y ago
Borg Backup (for similar reasons as Restic) essentially shifted backup from my "I-don't-but-I-should" list to my "solved problems" list. Is there anything similar for binary distribution? Here's what I mean. I
56.
by gsmecher 7y ago
These are all fair criticisms. Block designs, XML files for project and IP management, and auto-generated .tcl are all bad things. Eclipse sucks. I understand why vendors ship tools with all of these things. I think (hope?) they're slo
57.
by gsmecher 7y ago
It's not quite fair to say the tooling is flat-out awful. Vivado is much better than ISE. The place/route algorithms matured (analytical placement rather than simulated annealing), and the software it's wrapped in grew up (it
58.
by gsmecher 7y ago
Note that all of this is predicated on High Level Synthesis (HLS) becoming real, after many years of industry over-promises and under-deliveries. A jaded RTL engineer may fairly ask, "what's different this time?" I'm con
59.
by gsmecher 8y ago
The following paper is excellent and not totally irrelevant: http://home.agh.edu.pl/~turcza/sr/Splitting%20the%20Unit%20D... The effects you're describing (blurring, numerical stability) are readily formalize
60.
by gsmecher 8y ago
This is a great question but it's a little off-topic. I've been watching compressed sensing (CS) from the sidelines for the past decade, while wearing experimental-cosmology, synthetic-aperture RADAR, and instrumentation/FPGA

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