Tooling tends to stack vertically in software: you can put together Jython-on-JVM-in-Docker-on-Linux-in-EC2 if you want to, without every layer diminishing the

Tooling tends to stack vertically in software: you can put together Jython-on-JVM-in-Docker-on-Linux-in-EC2 if you want to, without every layer diminishing the ones above and below it. In EDA, tooling stacks horizontally. At minimum, I need a simulator and a synthesizer, and both need to support the same features for those features to be useful. Every tool or layer I add to my EDA stack erodes the feature set I am able to use for all of them. Encrypted IP? VHDL-2008? SystemVerilog? Only with a commercial simulator. Now you have to start squabbling over licenses, which is the same problem except you've traded technical limitations for economic ones. (edit: and paid 6 figures for the privilege.) All of this is a huge drag on productivity. It benefits only the big EDA incumbents (not even the FPGA manufacturers). If EDA tooling is going to improve, we need to change this dynamic. Until we do, adding layers to the tooling is a net loss except for a small sliver of the user community. (Typically the people who wrote it.)