gsmecher

6 ms·

1.
by gsmecher 6mo ago
If AI does anything to the EDA space, I hope it helps break the chokehold the "big 3" have on tooling. Any startup that threatens their dominance gets acquired and disappeared. I also hope this is coming anyway (see e.g.: KiCad ni
2.
by gsmecher 6mo ago
I love that VHDL formalizes Verilog's pragmatic blundering, but emphasizing delta-cycle ordering is "inside baseball" and IMO bad marketing. VHDL's approach is conceptually clean, but from a practical perspective, this o
3.
by gsmecher 8mo ago
Towards the end of my EE degree in the mid-2000s, I hoodwinked Ralph into dropping by my dingy east-Vancouver rental for a tech demo. I was trying to find a home for my thesis research project, which was a very niche-y DSP algorithm that ha
4.
by gsmecher 1y ago
There's nothing wrong with an open clone when everybody is acting in good faith. (In fact, "good faith" does not even necessarily mean "according to the letter of the law in $jurisdiction". Sometimes the law is an a
5.
by gsmecher 1y ago
Oh my - good find, and also, eek. Analogy: https://datasheet.lcsc.com/lcsc/2302211830_analogysemi-ADX11... TI: https://www.ti.com/lit/ds/symlink/ads1115.pdf Analogy's datasheet is d
6.
by gsmecher 2y ago
These experiments are always unique, and each is interesting in its own way. Can you comment on the use of asynchronous code rather than generators? For example, here's a throw-away example of a clock using generators and a syntax that
7.
by gsmecher 2y ago
I've pushed a couple of boulders up this particular hill, and none of them have stayed there. Trouble is, Python is a great stack for communicating with networked instrumentation - except when asyncio gets involved. And, talking with d
8.
Awaitless: Ipython and REPL and Coroutines – Suffering(github.com)
3 points by gsmecher 2y ago|1 comments
9.
by gsmecher 3y ago
You should talk with Metrics (metrics.ca), who are walking a similar path and have a few years' head start. They are a solid team and are likely to be open and friendly about their direction and challenges. Metrics has an independently
10.
by gsmecher 3y ago
The "language wars" narrative feels pretty played-out, so I'm not going to get drawn into it. In the software world everyone seems to recognize that different languages have different strengths, and that there's room for
11.
by gsmecher 3y ago
From 2020. This article is hagiography - while it's worth celebrating how far HDL has come, it's also worth looking into what's holding us back. Verilog is one of those things, so here's a short complaint. Modern Verilog
12.
by gsmecher 3y ago
Xilinx/AMD doesn't make overt donations any more AFAIK, but they still subsidize hardware as a loss leader and for academics. For example, academic groups can buy the RFSoC 4x2 board for $2149 USD, which is a small fraction of the
13.
by gsmecher 3y ago
I posted the Reddit link because it wasn't my insight - but I agree it's a dubious source. That doesn't make it wrong. (I'm not certain it's right, either - it's an interesting claim.) A RV32I core is easy to i
14.
by gsmecher 3y ago
> This is dead right, the enabling technologies like You fundamentally misunderstand. Soft core CPUs aren't enabling technologies and haven't been for decades. They are plumbing, like FIFO or SERDESes. You can't sell an FP
15.
by gsmecher 3y ago
According to a Reddit comment [1], this is the same MicroBlaze RTL with a RISC-V instruction decoder in front of it. This seems crazy from a let's-make-the-best-RISCV-core perspective, but that's never been Xilinx/AMD's
16.
by gsmecher 3y ago
> Depends on what AMD does with Xilinx. Currently the AMD/Xilinx dynamic seems to reverse this: "Depends on what Xilinx does with AMD". AMD's software roadmap for AI/datacentre leans heavily on Vitis (for softwar
17.
by gsmecher 3y ago
The integrated Ethernet switch is only as useful as its software stack - I say this after an excruciating decade with TI's Sitara devices (and the built-in CPSW ethernet switch.)
18.
by gsmecher 3y ago
On FPGAs, a register file probably fits better into distributed RAM than block RAM. On Xilinx, for example: a 64-bit register file doesn't map efficiently to Xilinx's RAMB36 primitives. You'd need 2 RAMB36 primitives to provi
19.
by gsmecher 3y ago
> What's your issue with Shockley btw? Nobody can pick fights with Shockley any more (he's dead) - but Shockley is almost a household name, and Bardeen/Brattain's aren't. It's worth trying to adjust the reco
20.
by gsmecher 3y ago
> everything comes down to datapath. Ain't that the truth. However: Xilinx's DSP58 blocks (Versal devices), and older Intel DSPs, do integrate floating point into the DSP tiles - which does narrow the gap between the datasheet&
21.
by gsmecher 3y ago
Also discussed here: https://old.reddit.com/r/FPGA/comments/15fnb6u/egpu_a_750_mh...
22.
by gsmecher 3y ago
Project X-Ray [1] and Project U-Ray [2] are the best source for configuration details that Xilinx/AMD doesn't publish. These projects focus, respectively, on the 7-series and UltraScale FPGAs. [1]: https://f4pga.readthe
23.
by gsmecher 3y ago
Interesting. If you ever do track down the scuttlebutt on poor-performance internal regulators, please pass it along? I'm not terribly hard to find.
24.
by gsmecher 3y ago
On the mystery voltage regulator: most OCXOs also provide a regulated reference output on the pin that's marked N/C on this device. This reference is important because the tuning voltage is scaled relative to some reference voltag
25.
by gsmecher 3y ago
The software/firmware/hardware stack is layered. Here's what has worked for me, for several FPGA-based instrumentation applications. * Integration level: this is typically Yocto or Buildroot. It's architected to want its
26.
by gsmecher 3y ago
Note that you can't compare LUT4 results (ZPU @ 440 LUTs) against LUT6 results (PicoRV32 @ 750 LUTs). The ZPU is remarkably small, and it's a bigger gap than a direct comparison shows. SERV is a fair comparison, since it's ar
27.
by gsmecher 3y ago
The ZPU may be smaller than you're crediting. 440 LUTs is very little space. The reported synthesis results ("440 LUTs") are on old Spartan-3 fabric. These are LUT4s, and anything from Xilinx newer than about 2006 uses much m
28.
by gsmecher 4y ago
It is wonderful to see open-source tooling continue to invade the EDA space. Two pieces of context for non-practitioners: First: the "slow" part of an HDL toolflow is synthesis/place-and-route, not elaboration or translation
29.
by gsmecher 4y ago
> As someone who's manufactured thousands of PCB designs, I couldn't disagree with this article/video more. I think you're vastly overstating how much "bad" advice there is in the video, and the degree to wh
30.
by gsmecher 4y ago
My best-in-class example of document management is Xilinx (now AMD). Internally, they use an XML flow based on DITA - but the specifics aren't nearly as important as an apparent organizational commitment to delivering quality documenta

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