gluggymug

16 ms·

91.
by gluggymug 11y ago
A fair bit harder unfortunately. You only have the core here. A regular microcontroller has a lot of necessary extras in there. You generally want modules to handle power and clock generation. Flash memory is usually in there to hold firmwa
92.
by gluggymug 11y ago
It is who you sell to. My sister went to HS with two brothers who trained as sculptors. They had to hustle for dumb jobs (like gates or repairing dumpsters) for a long time until they began to get work making interactive sculptures for play
93.
by gluggymug 11y ago
I saw a little info on that at https://github.com/ucb-bar/fpga-zynq I guess you are referring to that? It's supposed to be a relatively mature tool so there's got to be a version that works ok.
94.
by gluggymug 11y ago
I think I am one of those who would do it the other way around, from the outside inwards connecting to the outside world first. I already know ALL the I/O for the core is somewhere in the RISC-V design code (exact signal names etc). It
95.
by gluggymug 11y ago
There's two possibilities. - Rocket has no automated build flow that checks whether committed code is synthesizable. - you aren't using the same flow as them. I struggled to find what synthesis tools they used just now so I don&#x
96.
by gluggymug 11y ago
Firstly, I commend you on your work. Second, I looked into your tests directory and from first impressions there's not much there. What is there is kinda messy and not conducive to thorough testing. If I could make a suggestion: you sh
97.
by gluggymug 11y ago
You saying equivalence checking at each layer is not normal in commercial, SOC design? That it's essentially only the shops using the best EDA tools and such? We have a difference in terminology. Co-simulation and equivalence checkin
98.
by gluggymug 11y ago
It depends on the project. For SOCs that I was involved with (DSPs, mobile phone SOC, wifi SOC), you are bringing together a lot of different IP from various sources. There's no way to use these HLS tools unless the third parties feel
99.
by gluggymug 11y ago
That does sound like a good aspect of Chisel. How do they test that the Chisel RTL and the generated Verilog are equivalent though? To me I would want a good verification environment that tests one against the other. Testing just via loadin
100.
by gluggymug 11y ago
What do you think of that model vs exclusively leveraging HW people? Sounds good. Cheap fab I am not sure whether the costs make sense. Depends on the project I guess. I don't have a lot of experience with those manufacturing process
101.
by gluggymug 11y ago
(Yeah you can't reply straight away) Looking at a lot of stuff you referenced. I think my definition of tests is a lot more generic than yours. Taking a look at your links it seems tests are written in RISC-V machine code? The code wil
102.
by gluggymug 11y ago
Ok. If you do the majority of your testing on the generated Verilog, I am not sure what the point of the Chisel C++ cycle accurate simulator is. I thought that ran on the Chisel RTL. What simulator do you use to test the generated Verilog?
103.
by gluggymug 11y ago
How do I get my test stimulus into my simulator? And where is my checking? Hypothetically I wrote my tests and checkers in Chisel. I now want to run a gate level simulation of my tests. I asked the same thing to the Clash guys. Can it do th
104.
by gluggymug 11y ago
I think maybe the HLS can get you a core design but then when you try to use it and integrate into an FPGA you will have to deal with the low level issues of registers and combinatorial logic. This is fine for the experienced HW person, but
105.
by gluggymug 11y ago
how did the academics do it? Tape out using these tools? My guess is they skipped gate level and other stuff that I consider good quality (BISTs, DFT logic, power estimation etc). You either skip it or rewrite your tests in Verilog/V
106.
by gluggymug 11y ago
While describing the function of a circuit like MyHDL and many other languages have tried to do it cute, they have never come close to a real engineer I agree with you on that. For a beginner I think a high level language is the wrong dir
107.
by gluggymug 11y ago
I've been skimming through MyHDL stuff. It does support RTL like Chisel supposedly. http://docs.myhdl.org/en/latest/manual/rtl.html So it should simulate RTL and give you cycle accurate waves. No gate le
108.
by gluggymug 11y ago
I think it is a high level synthesis tool like a SystemC etc. My concern for a beginner would be how to get your high level design integrated into the FPGA. For a beginner, there are a lot of what-ifs that they are probably going to stumb
109.
by gluggymug 11y ago
Okay this is getting weird. I just read your link so this is all from my first impressions. MyHDL is talking about co-simulation on the gate-level netlist. They do not recommend it. However they say MyHDL can do co-simulation on Verilog RTL
110.
by gluggymug 11y ago
Just took at look at the cx-lang website. I think it may be too weird for a beginner looking for results. I've been in ASIC & FPGA engineering for 15+ years. The design flow I think they use is more like writing a program that gets
111.
by gluggymug 11y ago
You saying MyHDL is not cycle accurate? Could you give a citation for that?
112.
by gluggymug 11y ago
Learning by doing is cool. You don't have to do it the conventional way. It's just that from my perspective, I can only focus on the future problems. I am too traumatized from the HW experience! I almost rewrote a couple of my poi
113.
by gluggymug 11y ago
Tools vendors each have coding guidelines that their stuff likes. At the RTL level, industry guys like myself just follow them like puppies due to fear of something in the tool chain breaking. Then we complain to them when it misbehaves any
114.
by gluggymug 11y ago
Uh oh. I didn't realize you were actually on HN. Apologies if my other spiel seems too harsh. Perhaps the better sounding term would be "engineering practices" rather than "industry practices". If it's a hobby,
115.
by gluggymug 11y ago
Not a great codebase. That's putting it lightly. It does have a pipeline BTW. Industry is so different I don't know where to start complaining. Xilinx tools are not used for simulation usually because they suck and we generally pa
116.
by gluggymug 11y ago
I think you better get some interests. What's the point of free time otherwise? Or the savings?
117.
by gluggymug 11y ago
No commuting in traffic! (That's a joke for the Sydney-siders on HN) I essentially see myself as an early retiree so I live like a retired person. My parents became a bit of a template. The 8 or so hours of the day that I had to work a
118.
by gluggymug 11y ago
If your job is completely misaligned with your values, I think making a job change is a good idea. Don't do something that isn't you. Maybe it's my particularly uninteresting values but no job resonates that much. Even if it
119.
by gluggymug 11y ago
Perhaps I phrased it poorly. Is current work really that dull? I prefer to change the term being "slave to wage" to "I worked for a living". But everyone has different circumstances financially. If you are truly stuck in
120.
by gluggymug 11y ago
29 is a good age to be thinking about this. I have an alternate philosophy that doesn't make you quit your job to find yourself. See if it resonates with you. You can't be too emotionally attached to your job. Jobs have value but

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