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There's two possibilities. - Rocket has no automated build flow that checks whether committed code is synthesizable. - you aren't using the same flow as them.
by gluggymug 11y ago
There's two possibilities.
- Rocket has no automated build flow that checks whether committed code is synthesizable.
- you aren't using the same flow as them. I struggled to find what synthesis tools they used just now so I don't blame you!
- rjsw 11y agoThe code that is committed isn't directly synthesizable, it needs to be transformed to HDL by a tool that is itself being updated. I tried what looked to be a supported flow, generate Verilog for FPGAs then synthesize it for Xilinx Zynq devices. The Verilog errors looked correct to me.
- gluggymug 11y agoI saw a little info on that at https://github.com/ucb-bar/fpga-zynq https://github.com/ucb-bar/fpga-zynq I guess you are referring to that? It's supposed to be a relatively mature tool so there's got to be a version that works ok.