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Just took at look at the cx-lang website. I think it may be too weird for a beginner looking for results. I've been in ASIC & FPGA engineering for 15+ years. Th

Just took at look at the cx-lang website. I think it may be too weird for a beginner looking for results. I've been in ASIC & FPGA engineering for 15+ years. The design flow I think they use is more like writing a program that gets translated into hardware. Very different from the regular methodology. Sounds great but there's a big leap between that and getting your FPGA working. For a beginner, it's too much to take on. I think maybe Chisel and those others would be easier.

nickpsecurity 11y ago
Yeah, I was actually hoping it was a high-level synthesis tool. I appreciate your review on the ease-of-use aspect.
- gluggymug 11y ago
  I think it is a high level synthesis tool like a SystemC etc. My concern for a beginner would be how to get your high level design integrated into the FPGA. For a beginner, there are a lot of what-ifs that they are probably going to stumble on.
  - trsohmers 11y ago
    Chisel is not high level synthesis, which is one of the reasons why I love it. You are actually describing the circuit itself, with is what a hardware description language is supposed to do. While describing the function of a circuit like MyHDL and many other languages have tried to do it cute, they have never come close to a real engineer thinking of how to solve the problem with registers and combinational logic directly.
    - nickpsecurity 11y ago
      Of course it's not. That's why real HW types use it and people like me don't. ;) One of my goals on HW security side is to bring synthesis to a level that non-HW people can use it for an OK solution. I found Cx when looking at the awesome Qflow method and tools. Since you post a lot, what's your opinion on Cx as a HLS tool for programmers without expertise as HW engineers? And outside big EDA, what is your recommendation for lowest cost vs effectiveness HLS for those wanting to clean-slate their hardware or at least accelerate things on FPGA's?
    - gluggymug 11y ago
      While describing the function of a circuit like MyHDL and many other languages have tried to do it cute, they have never come close to a real engineer I agree with you on that. For a beginner I think a high level language is the wrong direction to go because it's taking them further away from the method of designing a HW solution. It's adding another layer of abstraction.
      - nickpsecurity 11y ago
        That's what people said about going to 3GL's. I'm glad, for my day-to-day computing, that most went in the other direction (pro 3GL's). Software people can't get the kind of results hardware people can while using HLS techniques. That's obvious. Yet, the existing research shows they should be able to get quite a bit of results with little knowledge of hardware. EDA tools actually solved most of the hard parts. Only thing that's lacking are tools to accomplish this and at prices most people can afford. Two paths developed in parallel. One for those trying to boost their software with hardware generation. One for hardware designers trying to improve their own craft. And with the benefit that one's tools can integrate the other. Best of both worlds. So, I look for both.
        gluggymug 11y ago
        I think maybe the HLS can get you a core design but then when you try to use it and integrate into an FPGA you will have to deal with the low level issues of registers and combinatorial logic. This is fine for the experienced HW person, but not for the beginner. In other words, the HLS is better for the experienced HW designer than the beginner even though it looks like its easy. Unfortunately there is no infrastructure for you to build onto. It's like a blank slate. All the I/O needs to be done right. It's very seldom just instantiating wires unless your design is blazingly simple. And if it were simple you wouldn't need an FPGA in the first place. A generic coprocessor would kick most FPGAs butts.
        nickpsecurity 11y ago
        Ok that all makes more sense. One of my potential flows was actually having the amateurs build lost of functionality (eg accelerators, device protocols) with HLS tools that a hardware engineer could finalize for FPGA. Would save on the rare labor. What do you think of that model vs exclusively leveraging HW people? Far as ASIC's, I'd just get HW people, haggle on the tools, use free one's if possible (see Qflow), and do a MPW run for prototyping/production. eASIC's 90nm maskless stuff, potentially. Start it on 180nm-350nm, though, as there's lots of cheap masks and fab capacity there.
    - jandecaluwe 11y ago
      You have it completely backwards. The best "real engineers" do not "think directly" on how to solve the problem with registers and combinational logic. They think about how to solve the problem functionally and let synthesis take care of the logic as much as possible. MyHDL is ideal for that. That is how ASICs/FPGAs have been designed by the best teams for the last 2 decades. And it is much more productive than the textual schematic entry you are describing. There is simply no comparison. Synthesis works. As for your word-playing attempt: "description" stands for a number of things, among those "describing behavior". Just check the Verilog/VHDL LRM or MyHDL manual.
      - nickpsecurity 11y ago
        Exactly. It's crazy to even think, outside of analog, that someone would want to build a modern SOC with RTL directly. Even the full-custom folks like Intel, correct me if I'm wrong, essentially use a hardware approach where they can abstract away from and use EDA to synthesize to the stuff they hand-craft. Most SOC builders simply don't have the labor to waste working at RTL for a complex design & its inevitable problems. It's why they pay so much to the Big Three for synthesis tools. For software people following, it would be like trying to build Microsoft Word with assembler while competition was using C/C++. Note: Chuck Moore of Forth fame may be the exception to this rule in SOC design. Then again, he's an exception to a lot of them. ;) http://www.ultratechnology.com/okad.htm http://www.ultratechnology.com/okad.htm
        gluggymug 11y ago
        It depends on the project. For SOCs that I was involved with (DSPs, mobile phone SOC, wifi SOC), you are bringing together a lot of different IP from various sources. There's no way to use these HLS tools unless the third parties feel like writing a model for their IP in your choice of HLS tool language. This means you would have gaps in your HL design everywhere their stuff fits in. Verification in the high level language would be tough work until those gaps are filled. No doubt guys like Intel can use the fancy HLS tools on their SOC because they own every module in the design. Same goes for the RISCV stuff: They can run Chisel sims because they wrote every part of the design in Chisel. The rest of us idiots are doing straight Verilog RTL because SOC level is more about gluing a lot of different modules together with low level logic. Maybe there's a tool here or there that generates a little Verilog from some other language for you but that is very piecemeal. It really is like building Word with assembler. But your job is more about linking together static libraries that already work. It's grunt work and nothing special. Being able to discover a bug via verification is the skillful part. This is where the cosimulation that MyHDL supports is so handy. Reading up on it a bit more, it sounds very promising for the future. The Verilog RTL parts run in the Verilog simulator while the MyHDL parts run in the MyHDL simulator.

nickpsecurity 11y ago

Yeah, I was actually hoping it was a high-level synthesis tool. I appreciate your review on the ease-of-use aspect.

gluggymug 11y ago
I think it is a high level synthesis tool like a SystemC etc. My concern for a beginner would be how to get your high level design integrated into the FPGA. For a beginner, there are a lot of what-ifs that they are probably going to stumble on.
- trsohmers 11y ago
  Chisel is not high level synthesis, which is one of the reasons why I love it. You are actually describing the circuit itself, with is what a hardware description language is supposed to do. While describing the function of a circuit like MyHDL and many other languages have tried to do it cute, they have never come close to a real engineer thinking of how to solve the problem with registers and combinational logic directly.
  - nickpsecurity 11y ago
    Of course it's not. That's why real HW types use it and people like me don't. ;) One of my goals on HW security side is to bring synthesis to a level that non-HW people can use it for an OK solution. I found Cx when looking at the awesome Qflow method and tools. Since you post a lot, what's your opinion on Cx as a HLS tool for programmers without expertise as HW engineers? And outside big EDA, what is your recommendation for lowest cost vs effectiveness HLS for those wanting to clean-slate their hardware or at least accelerate things on FPGA's?
  - gluggymug 11y ago
    While describing the function of a circuit like MyHDL and many other languages have tried to do it cute, they have never come close to a real engineer I agree with you on that. For a beginner I think a high level language is the wrong direction to go because it's taking them further away from the method of designing a HW solution. It's adding another layer of abstraction.
    - nickpsecurity 11y ago
      That's what people said about going to 3GL's. I'm glad, for my day-to-day computing, that most went in the other direction (pro 3GL's). Software people can't get the kind of results hardware people can while using HLS techniques. That's obvious. Yet, the existing research shows they should be able to get quite a bit of results with little knowledge of hardware. EDA tools actually solved most of the hard parts. Only thing that's lacking are tools to accomplish this and at prices most people can afford. Two paths developed in parallel. One for those trying to boost their software with hardware generation. One for hardware designers trying to improve their own craft. And with the benefit that one's tools can integrate the other. Best of both worlds. So, I look for both.
      - gluggymug 11y ago
        I think maybe the HLS can get you a core design but then when you try to use it and integrate into an FPGA you will have to deal with the low level issues of registers and combinatorial logic. This is fine for the experienced HW person, but not for the beginner. In other words, the HLS is better for the experienced HW designer than the beginner even though it looks like its easy. Unfortunately there is no infrastructure for you to build onto. It's like a blank slate. All the I/O needs to be done right. It's very seldom just instantiating wires unless your design is blazingly simple. And if it were simple you wouldn't need an FPGA in the first place. A generic coprocessor would kick most FPGAs butts.
        nickpsecurity 11y ago
        Ok that all makes more sense. One of my potential flows was actually having the amateurs build lost of functionality (eg accelerators, device protocols) with HLS tools that a hardware engineer could finalize for FPGA. Would save on the rare labor. What do you think of that model vs exclusively leveraging HW people? Far as ASIC's, I'd just get HW people, haggle on the tools, use free one's if possible (see Qflow), and do a MPW run for prototyping/production. eASIC's 90nm maskless stuff, potentially. Start it on 180nm-350nm, though, as there's lots of cheap masks and fab capacity there.
  - jandecaluwe 11y ago
    You have it completely backwards. The best "real engineers" do not "think directly" on how to solve the problem with registers and combinational logic. They think about how to solve the problem functionally and let synthesis take care of the logic as much as possible. MyHDL is ideal for that. That is how ASICs/FPGAs have been designed by the best teams for the last 2 decades. And it is much more productive than the textual schematic entry you are describing. There is simply no comparison. Synthesis works. As for your word-playing attempt: "description" stands for a number of things, among those "describing behavior". Just check the Verilog/VHDL LRM or MyHDL manual.
    - nickpsecurity 11y ago
      Exactly. It's crazy to even think, outside of analog, that someone would want to build a modern SOC with RTL directly. Even the full-custom folks like Intel, correct me if I'm wrong, essentially use a hardware approach where they can abstract away from and use EDA to synthesize to the stuff they hand-craft. Most SOC builders simply don't have the labor to waste working at RTL for a complex design & its inevitable problems. It's why they pay so much to the Big Three for synthesis tools. For software people following, it would be like trying to build Microsoft Word with assembler while competition was using C/C++. Note: Chuck Moore of Forth fame may be the exception to this rule in SOC design. Then again, he's an exception to a lot of them. ;) http://www.ultratechnology.com/okad.htm http://www.ultratechnology.com/okad.htm
      - gluggymug 11y ago
        It depends on the project. For SOCs that I was involved with (DSPs, mobile phone SOC, wifi SOC), you are bringing together a lot of different IP from various sources. There's no way to use these HLS tools unless the third parties feel like writing a model for their IP in your choice of HLS tool language. This means you would have gaps in your HL design everywhere their stuff fits in. Verification in the high level language would be tough work until those gaps are filled. No doubt guys like Intel can use the fancy HLS tools on their SOC because they own every module in the design. Same goes for the RISCV stuff: They can run Chisel sims because they wrote every part of the design in Chisel. The rest of us idiots are doing straight Verilog RTL because SOC level is more about gluing a lot of different modules together with low level logic. Maybe there's a tool here or there that generates a little Verilog from some other language for you but that is very piecemeal. It really is like building Word with assembler. But your job is more about linking together static libraries that already work. It's grunt work and nothing special. Being able to discover a bug via verification is the skillful part. This is where the cosimulation that MyHDL supports is so handy. Reading up on it a bit more, it sounds very promising for the future. The Verilog RTL parts run in the Verilog simulator while the MyHDL parts run in the MyHDL simulator.