I think I am one of those who would do it the other way around, from the outside inwards connecting to the outside world first. I already know ALL the I/O for t

I think I am one of those who would do it the other way around, from the outside inwards connecting to the outside world first. I already know ALL the I/O for the core is somewhere in the RISC-V design code (exact signal names etc). It has to be in Chisel or something. I would translate that to VHDL to get my ports. It becomes a stub to build my core-level testbench on. If I can mirror their test environment, I at least have a start point. Maybe I could even reuse their testbench somehow. Then I'd start duplicating the sub modules and their interconnections in the core. And so on. Do the tough stuff first then enjoy things getting easier as I go along hopefully!