avianes

9 ms·

31.
by avianes 4y ago
When I have to explain the speed of a processor to a neophyte I always begin by avoiding using GHz unit which has the weakness of hiding the magnitude of the number, so I explain things in terms of billions of cycles each second. As an exam
32.
by avianes 4y ago
Not a cryptography specialist, but I doubt that all crypto algorithms have the same property of causing 0s (or 1s) to massively appear for some inputs in a way that could lead to a key leakage with this attack. I believe that SIKE is an ext
33.
by avianes 4y ago
SIKE is definitely not the most widely used cryptographic algorithm. And as the paper points out: > In our attack, we show that, when provided with a specially-crafted input, SIKE’s decapsulation algorithm produces anomalous 0 values tha
34.
by avianes 4y ago
I see nobody pointing out the relatively low number of integer registers (32 64-bit registers [1]) for a VLIW that is intended to emulate an high-end Out-of-Order machine. Modern high-end Out-of-Order processors feature over 160 physical in
35.
by avianes 4y ago
> Nowhere on Earth, will you find an organization that will execute both sides of a conditional process requiring hunans to do the work just to throw away the result. Not taken. Speculative execution today (within modern high-end process
36.
by avianes 4y ago
I'm not sure if this answers your question but VLIW processors feature speculative loads. "speculative load" can be seen as data prefetch to a register, but with a extra instruction to put before reading/using the regist
37.
by avianes 4y ago
I do not understand how you want to mitigate this issue by using the "context" given that the attack demonstration is done with a source code that makes use of the "context". The attack is fully context-agnostic since th
38.
Spectre Attacks on Apple Silicon [pdf](misc0110.net)
1 points by avianes 4y ago|0 comments
39.
by avianes 4y ago
Pine64 is based on an Allwinner A64 which has a ARM GIC-400. ARM GIC-400 is a standard GIC IP from ARM and compliant with ARM GICv2 specification. It seems pretty standard to me, not a custom GIC as Apple. And yes, in u-boot there are plent
40.
by avianes 4y ago
This is not true. Most manufacturers take standardized IP and IP-providers provide an appropriate linux drivers. Few manufacturers are willing to develop and maintain their own GIC hardware and GIC driver, most of the time they just take th
41.
by avianes 4y ago
Are you confusing "amd64" with "Aarch64"? "amd64" has nothing to do with Macs/Apple products. Anyway, both amd64 and Aarch64 are already being used outside of Macs/Apple products.
42.
by avianes 4y ago
ISA does matter in a CPU design and CPU performance: - Variable instruction sizes make the front-end more complex and limits the decoding width; - Delayslot makes superscalar front-end more complex; - Page size limits VIPT L1 cache size; -
43.
by avianes 4y ago
It all depends on your definition of "secure". - What kind of attack do we need to prevent? - What do we need to be protected from? - What do we not need to be protected from? All of this (and more) must be defined in your threat
44.
by avianes 4y ago
> I thought this attack vector was pretty well known Yes, fault attacks are well known, but this paper is about software-based fault attacks. And as discussed in section I.A), the various integrity check mechanisms of SGX were believed t
45.
by avianes 4y ago
While I agree that the RISC-V V extension is questionable, it does not necessarily make decoding into uop more complex. When the vector register is allocated there is a known vector register size, and we have then 3 ways to go: 1) Producing
46.
by avianes 4y ago
Little addendum: Macro-op fusion (alone) does not only reduce the number of uop, it could also reduces physical register usage as intermediate results are not stored into physical registers. For instance, the indexed load pattern (ADD+LOAD)
47.
by avianes 4y ago
> High end cores want to split everything up (RISC-V comes pre-split) Yes but a high-end core does not necessarily splits instruction the same way as RISC-V does. For instance an indexed store: RISC-V ISA splits it into an ADD+STORE pa
48.
by avianes 4y ago
> I think what Jha was questioning was whether catching up to ARM is feasible if your main weapon is macro-op fusion. I don't think so, there are indeed unrealistic macro-op fusion patterns that can reasonably be described as &quo
49.
by avianes 4y ago
I talk about feasibility , not about design win in a high perf. circuit, since there is no real high perf. RISC-V today and since it's the feasibility that is questioned by the parent. I can't say if the macro-op fusion will be
50.
by avianes 4y ago
> lot of the design rides on "oh we're just going to combine all the very RISC instructions into macro-ops to catch up to what ARM is doing" There are more macro-op fusion suggestions for RISC-V precisely because RV instru
51.
by avianes 4y ago
And because we KNOW about the Intel ME many security researchers have been looking for backdoors and vulnerabilities in it, several vulnerabilities have been found but no backdoor. If Intel wants to put a backdoor ME would probably be a bad
52.
by avianes 4y ago
I'm not really optimistic about the hardware and the tape-out goal. The author seems to have a very basic knowledge about it. For instance, the int multiplier design is overengineered, very naive and far from state of the art (no pipel
53.
by avianes 5y ago
Of course things could have moved, the area was active. You can check out this thread [1] from bellingcat which shows pictures and videos of this place. And you can clearly see that there is more than one corpse. [1]: https://twi
54.
by avianes 5y ago
> Building on the left is of another form You can check with google map for example at "50.54124726729443, 30.228596257255703" (and looking towards south-west). You will see both the satellite view and street-view matches with
55.
by avianes 5y ago
The volatile keyword in C has nothing to do with cache coherence and does not prevent cache coherence issues. It just forces the compiler to generate all memory accesses on this variable. And if this variable is in a cached memory region, t
56.
by avianes 5y ago
RISC-V is an open and royalty free ISA, it can't really be backdoored. And several Chinese companies are working on RISC-V implementation
57.
by avianes 5y ago
I see, there are indeed solutions like regfile duplication to handle large port number but it's expensive when physical regfile becomes large. I still think that the uarch's job is to ensure minimal implementation cost ;). Thank y
58.
by avianes 5y ago
Yes, the "dual register file" is probably the most intriguing to me. This looks like a renaming scheme used in some old micro-architecture (Intel Core 2 maybe) where ROB receives transient results and acts as a physical regfile, a
59.
by avianes 5y ago
Yes, there is a huge lack of open and approachable information sources in micro-architecture. Be aware though, the micro-architecture used here is very interesting but differs in many ways from state of the art industrial high-end micro-arc
60.
by avianes 5y ago
We don't need indexed loads only for loops. But even within loops, you may need indexed load. One simple example: when you do loop unrolling, you must access elements n+4, n+8 and n+12 etc.

More ›