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I talk about feasibility, not about design win in a high perf. circuit, since there is no real high perf. RISC-V today and since it's the feasibility that is qu

I talk about feasibility, not about design win in a high perf. circuit, since there is no real high perf. RISC-V today and since it's the feasibility that is questioned by the parent. I can't say if the macro-op fusion will be enough to beat ARM & x86, but I can tell it's feasible.

kragen 4y ago
What do you mean by "implemented"? Clearly macro-op fusion is a computable transformation of the instruction stream, so macro-op fusion is certainly feasible. I think what Jha was questioning was whether catching up to ARM is feasible if your main weapon is macro-op fusion. The Celio/Dabbelt/Patterson/Asanović tech report I linked yesterday shows that it's promising, but it's been six years and I'd like to know if that's actually being tried and how well it works. Bruce Hoult's comment from a few months ago suggests that it wasn't really being tried at SiFive, but he left SiFive a couple years ago and might be out of date, and the Honey Badger designs are potentially a whole new ballgame.
- avianes 4y ago
  > I think what Jha was questioning was whether catching up to ARM is feasible if your main weapon is macro-op fusion. I don't think so, there are indeed unrealistic macro-op fusion patterns that can reasonably be described as "unfeasible" or "unrealistic". But macro-op fusion patterns suggested in the RISC-V spec, papers about macro-op fusion on RISC-V, and the SiFive patent on macro-op fusion are realistic and feasible. > Bruce Hoult's comment from a few months ago suggests that it wasn't really being tried at SiFive Commits from SiFive people's in GCC [1] suggest that short-forward-branch macro-op fusion patterns are recognized by SiFive hardware. I don't know if they recognize other macro-op fusion patterns. But SiFive has a bunch of stuff to improve before diving into macro-op fusion. [1]: https://patchwork.ozlabs.org/project/gcc/patch/20190430234741.8120-1-jimw@sifive.com/ https://patchwork.ozlabs.org/project/gcc/patch/2019043023474...
  - kragen 4y ago
    Yes, that's the macro-op fusion pattern Hoult said they were recognizing in his post.

kragen 4y ago

What do you mean by "implemented"? Clearly macro-op fusion is a computable transformation of the instruction stream, so macro-op fusion is certainly feasible. I think what Jha was questioning was whether catching up to ARM is feasible if your main weapon is macro-op fusion. The Celio/Dabbelt/Patterson/Asanović tech report I linked yesterday shows that it's promising, but it's been six years and I'd like to know if that's actually being tried and how well it works. Bruce Hoult's comment from a few months ago suggests that it wasn't really being tried at SiFive, but he left SiFive a couple years ago and might be out of date, and the Honey Badger designs are potentially a whole new ballgame.

avianes 4y ago
> I think what Jha was questioning was whether catching up to ARM is feasible if your main weapon is macro-op fusion. I don't think so, there are indeed unrealistic macro-op fusion patterns that can reasonably be described as "unfeasible" or "unrealistic". But macro-op fusion patterns suggested in the RISC-V spec, papers about macro-op fusion on RISC-V, and the SiFive patent on macro-op fusion are realistic and feasible. > Bruce Hoult's comment from a few months ago suggests that it wasn't really being tried at SiFive Commits from SiFive people's in GCC [1] suggest that short-forward-branch macro-op fusion patterns are recognized by SiFive hardware. I don't know if they recognize other macro-op fusion patterns. But SiFive has a bunch of stuff to improve before diving into macro-op fusion. [1]: https://patchwork.ozlabs.org/project/gcc/patch/20190430234741.8120-1-jimw@sifive.com/ https://patchwork.ozlabs.org/project/gcc/patch/2019043023474...
- kragen 4y ago
  Yes, that's the macro-op fusion pattern Hoult said they were recognizing in his post.