avianes

13 ms·

61.
by avianes 5y ago
> Go take a look at a lot of C code (hint, look at SPEC benchmarks). They do that. This does not really justify isolating that snippet if you admit yourself it's a bad one. > The sins of the original RISC-V was spending too much
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by avianes 5y ago
> This biggest issue is one instruction spanning two cache lines Even with fixed (32 bit) instruction lengths aligned on 32 bit, when we have to decode a group of 8 instructions you are facing this kind of issue. So you either have to cu
63.
by avianes 5y ago
To clarify, I'm not saying that RISC-V code density of C extension is a big advantage over its competitors, but it is a huge benefit for RISC-V. You are right, code density is perhaps not that critical today. And it is difficult to qua
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by avianes 5y ago
The encoding space is not the number of bits used to encode an instruction, the encoding space is the ratio of values that encode a valid instructions over the total number of instructions that could be encoded. As an example, in an ISA wit
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by avianes 5y ago
Yes, but RISC-V still has a lot of encoding-space free and the benefit of C extension is huge. It's a trade-off. I don't think RISC-V is perfect or universal, but on this point they do a pretty good job compared to other ISAs
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by avianes 5y ago
You are right but RISC-V variable instruction size is indeed a good trade-off. Unlike x86 where instructions can range from 1 up to 15 byte, current RISC-V ISA only has 2 instruction sizes. Today x86 decoding is limiting because we want to
67.
by avianes 5y ago
Variable instruction sizes have a cost, but with only 2 instruction sizes like current RISC-V that cost remains very low as long as we don't have to decode a very large number of instructions each cycle, and it gives a huge code densit
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by avianes 5y ago
Why using an unsigned? It is obvious here that RISC-V without Zba takes 4 instructions because it manages special cases related to unsigned. If you use a simple int for index: slli a1,a1,2 add a0,a0,a1 lw a0,0(a0) And isola
69.
by avianes 5y ago
> and the released C906 Verilog code might have some updates and bugfixes compared to the silicon in the D1 Not really, the C906 source code (close-source) is written in Vperl (a custom internal language) which is translated into verilog
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by avianes 5y ago
> Is the openc906 definitely the same design No, OpenC906 is a light version of the C906 and they only release generated verilog code without any testbench
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by avianes 5y ago
XuanTie C906 is not open-source. They just open-source a light version of the C906, the OpenC906. For instance OpenC906 does not contain the vector extension. But even the OpenC906 is only partially open-source. They only disclosed verilog
72.
by avianes 5y ago
If NVIDIA's firmware's signature private keys are in a standard file instead of being in a HSM (Hardware Security Module), as all serious companies do, then NVIDIA can only blame themselves. I seriously doubt that firmware's
73.
by avianes 5y ago
AMD cannot just take or copy it. But they can indirectly take advantage of techniques that will be leaked. For example, we know that NVIDIA's SM are split into slice which allows to easily adjust the size of a SM without rewriting the
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by avianes 5y ago
Not sure if hackers understand that NVIDIA is not necessarily the only victim if they leak the hardware. This hardware folder potentially contains IPs from other companies and the standard cell library from TSMC
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Remote Memory-Deduplication Attacks [pdf](arxiv.org)
2 points by avianes 5y ago|0 comments
76.
by avianes 5y ago
> RISC-V is a competitor to Intel. If successful RISC-V threatens to not only take market share from Intel, but turn the entire market away from proprietary CPU's that are Intel's bread and butter. No, RISC-V is not a competito
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by avianes 5y ago
Itanium is based on the EPIC architecture (not to be confused with AMD's EPYC processors) which is an evolution of the VLIW architecture. VLIW architectures are based on the idea that instruction scheduling should be fully done at comp
78.
by avianes 5y ago
The original source does not claim that, it's a deformation from Tomshardware. Original claim [1]: > IFS is the only foundry to offer IP optimized for all three of the industry’s leading ISAs: x86, Arm and RISC-V. It's not the
79.
by avianes 5y ago
> I remove the apps after my trip So maybe it's not just the apps that make a difference, it could also be your location. Your battery can drain faster when your phone is searching more frequently for a cell signal. And this can hap
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by avianes 5y ago
Not if they break US patents (which is likely), or if the US puts more constraints on imports.
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by avianes 5y ago
> Having a hot centre is a terrible idea for anyone using a mouse because you have to carefully move the mouse into the centre of the display with precision and accuracy. It's even worse than "just" moving the mouse to the
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by avianes 5y ago
Whatever the target processor is, when we need performance we recompile for that specific target. And whatever the target processor is, if you need portability you compile only with extensions widely used. It's the exact same problem w
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by avianes 5y ago
> Some critique may come from wrong assumptions, but being critical is not just bashing Focusing criticism only on this architecture, producing criticism without any solid argument, putting aside all the positive aspects, criticism when
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by avianes 5y ago
> But the truth is that if you can build a CPU that fetches an infinite number of instructions per cycle, your biggest bottleneck isn't going to be the number of instructions, it's going to be unpredicted branches Note that: Wi
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by avianes 5y ago
The first answer is very poor and weak. > It still concentrates on fixing those problems that we had in 1980s (making instruction set that is easy to pipeline with a simple pipeline), but we mostly don’t have anymore This criticism is hi
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by avianes 5y ago
I see that you are pretty active here in debunking anti-RISC-V attacks, thanks for that! There are a bunch of poor criticisms about RISC-V. > This is something you've been told elsewhere in the discussion, but that you chose to igno
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by avianes 5y ago
I have an honest question, do you feel you are saving time? And if so, is this really the case? Having clever code proposals is surely a big advantage and seems to be a big time saver. But it also means that you have to constantly switch be
88.
by avianes 5y ago
> BTW, not sure if it was just auto-correct, but you mean “warp” and not “wrap”, right? Oh, sorry I totally meant "warp" not "wrap", I don't know how I introduced that typo. > It seems like you’re making the c
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by avianes 5y ago
The term "vector processor" generally refers to a processor with a traditional programming model, but which features a "vector" unit capable of performing operations on large vectors of fixed or variable size. It can occ
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by avianes 5y ago
SIMT is a programming model, you are right. But in the literature the term "SIMT architecture" is used to describe architectures optimized for the SIMT programming model. Just search for "SIMT architecture" in google sch

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