I'm not really optimistic about the hardware and the tape-out goal. The author seems to have a very basic knowledge about it. For instance, the int multiplier

I'm not really optimistic about the hardware and the tape-out goal. The author seems to have a very basic knowledge about it. For instance, the int multiplier design is overengineered, very naive and far from state of the art (no pipeline, no adder compressor). I would suggest the author to check wallace tree multiplier. But at this stage it would be preferable to use the native verilog multiply or a DSP macro to target FPGA for prototyping, and to focus the SIMT architecture and the pipelining. Arithmetic unit design is a science in its own. However it's a beautiful project!