I'm not sure if this answers your question but VLIW processors feature speculative loads. "speculative load" can be seen as data prefetch to a register, but wi

I'm not sure if this answers your question but VLIW processors feature speculative loads. "speculative load" can be seen as data prefetch to a register, but with a extra instruction to put before reading/using the register. This instruction check that the memory content has been received, otherwise the instruction stall the pipeline. It allows to reorder a load before a conditional branch. To determine whether the load has been received, there is an additional structure in the microarchitecture that tracks speculative loads in-flight. When a context switch occurs, this data-structure is overwritten, so there are additional mechanisms to replay the load in such cases.