_chris_

23 ms·

181.
by _chris_ 11y ago
This is why they have a RISC-V foundation, made up of big and small companies (Google, Oracle, HPE, etc.). Most (all?) of the RISC-V ISA is stuff that is out of patent and has a lineage going back more than 20 years. This issue is definitel
182.
by _chris_ 11y ago
https://github.com/ucb-bar/riscv-torture , stupid copy/paste.
183.
by _chris_ 11y ago
> Is there any one in the community who is actively working on the verification story ? Not sure. I'd look out for videos to show up at the RISC-V workshop that's ongoing ( http://riscv.org/workshop-jan2016.html
184.
by _chris_ 11y ago
A privileged spec is available, although it's not frozen yet. A Linux port already exists.
185.
by _chris_ 11y ago
You can get a commit log (PC, inst, write-back address, write-back data) from Rocket to compare against Spike's commit log. It's not documented because the verification story is still in flux, and the commit log is fairly manual (
186.
by _chris_ 11y ago
I've talked with them in person at the RISC-V workshops. But for better proof, Slide 35: http://riscv.org/workshop-jun2015/riscv-intro-workshop-june2...
187.
by _chris_ 11y ago
"With lowRISC, we hope to discuss at the upcoming RISC-V workshop (this Tuesday and Wednesday) the status of BOOM, and whether it will make sense to use it as our application cores." Hi Alex, I look forward to chatting with you gu
188.
by _chris_ 11y ago
Berkeley has done 11+ tape-outs of RISC-V chips. LowRISC is looking to do a silicon run in a year-ish, and there's already one company that's publicly stated they've already been shipping RISC-V cores in their cameras.
189.
by _chris_ 11y ago
It's a work-in-progress. But yes, expect it to happen Sometime (tm).
190.
by _chris_ 11y ago
RISC-V is a standard. Anybody can implement a CPU with the standard and then do whatever they want with that CPU. There are plenty of open-sourced RISCV cores already. Copyleft vs copyright is only an issue regarding how much of the extra &
191.
by _chris_ 11y ago
It's both increased bandwidth and lower energy. It'd be useless if it blew the thermal budget to achieve the higher bandwidth.
192.
by _chris_ 11y ago
This paper uses the open-source Rocket-chip processor ( https://github.com/ucb-bar/rocket-chip ), which is the same processor being used (and modified) by lowRISC. So hopefully you can buy RISC-V in the not-to-distant f
193.
by _chris_ 11y ago
I think it's pretty cool that the processor core used here is the same open-source RISC-V core being used by lowRISC.
194.
by _chris_ 11y ago
"The other thing I know is forbidden seems far more innocuous. You’re not allowed to say “roger”." Huh? Roger and Wilco are said all the time in real life (obviously not an appropriate response to all ATC requests, but far from fo
195.
by _chris_ 11y ago
Yah, the author does a follow-up blogpost (albeit, only a few days later, and not years, hehe). http://yosefk.com/blog/high-level-cpu-follow-up.html
196.
by _chris_ 11y ago
"Each school’s score is based on its number of publications and citations as well as its global and regional research reputation." Oh lord... one is easy to game, and the other is a self-fulfilling prophecy.
197.
by _chris_ 11y ago
2008? So... anything happen since? I assume nobody took him up on his offer! "Alan Kay: [...] "Just as an aside [...] a benchmark from 1979 at Xerox PARC runs only 50 times faster today. Moore’s law has given us somewhere between
198.
by _chris_ 11y ago
You should read through the RISCV mailing list archives ( https://lists.riscv.org/lists/ ) for discussions on these topics, and contribute your own thoughts if they haven't been covered. The ISA-dev list should be t
199.
by _chris_ 11y ago
You can find your answers in the Privileged ISA spec ( http://riscv.org/download.html#tab_spec_privileged_isa ). Of course, it's an open ISA, so you can do whatever you want. The style of virtual memory you choose to us
200.
by _chris_ 11y ago
"E.g. You have to compile a test and create a mechanism to load the binary into your testbench memory or whatever." God, that's always the hardest part about these things. The core takes you a weekend, but the connection to t
201.
by _chris_ 11y ago
Sure, I don't mean to suggest there aren't valid reasons for writing cores in VHDL, etc., I just want to clarify that Chisel (unlike say Verilog) will, by fiat, only ever generate synthesizable code. If that's ever not the c
202.
by _chris_ 11y ago
Then please submit an issue to the github issue queue. Don't complain on some internet forum and hope that somebody will read your mind. It works fine for me.
203.
by _chris_ 11y ago
The RISC-V ISA manual covers your question on page 37 (riscv.org). > "a split organization increases the total number of registers accessible with a given instruction width, simplifies provision of enough regfile ports for wide supe
204.
by _chris_ 11y ago
Chisel by definition can ONLY generate synthesizable Verilog.
205.
by _chris_ 11y ago
It's actually really pretty easy to do. I put together a handful of different RISC-V cores that all implement the privileged/supervisor spec ( https://github.com/ucb-bar/riscv-sodor/blob/master/s
206.
by _chris_ 11y ago
Slide 35 from the RISC-V workshop ( http://riscv.org/workshop-jun2015/riscv-intro-workshop-june2... ). I've also personally talked with some of the engineers who have shipped RISC-V cores in their products. The issu
207.
by _chris_ 11y ago
There already are shipping, commercial RISC-V cores. The end-products are things like cameras though, so they're not very likely to make the tech blog rounds.
208.
by _chris_ 11y ago
The real solution is the local library needs to offer coffee.
209.
by _chris_ 12y ago
Their github page is here ( https://github.com/lowrisc ). For example, here's the code to the Rocket processor ( https://github.com/lowRISC/rocket ), which is a fork from Berkeley's ( https:&#x2
210.
by _chris_ 12y ago
"More to the point, loop buffers and µop caches on the last couple generations of processors make encoding density mostly irrelevant to performance" As in, the part where x86 processors get to fully enable the "operate as a R

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