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I believe Jan Gray was only implementing RV32I, but he was manually laying out the core and the router himself! You can find his slides here (http://riscv.org/
by _chris_ 11y ago
I believe Jan Gray was only implementing RV32I, but he was manually laying out the core and the router himself!
You can find his slides here (http://riscv.org/workshop-jan2016.html http://riscv.org/workshop-jan2016.html).
- nickpsecurity 11y agoThanks for the link! re cores They don't appear to have floating point. That a pre-requisite for quite a few accelerator cases. Also could help explain how many he fits in there at what performance. re FPGA BOOM! I was thinking it was an UltraScale or Achronix given the numbers. So, that was a hit. re NOC Probably the most exciting thing there. I'm guessing he's going to license it. Might be able to use it in open projects or even ASIC's depending. I lack the expertise to speak on the latter except to say that the existence of EDA companies specializing in NOC generation means such a thing might be useful. Also, good to know we can hit this kind of performance on an UltraScale. Makes me more hopeful about what can be achieved with an open 45nm or 28nm FPGA once we get them. Archipelago is progress in that area at 45-65nm already.
- tacos 11y agoThat's the 32 bit integer subset, floating point is available. Plenty of stuff can get away with integer-only. Massive numbers of Xilinx DSP48 on a FPGA is pretty common.