I'm not sure this should be called "RISC". It seems very tightly coupled to the particular processor pipeline being proposed: It has dynamic typing (each regis

I'm not sure this should be called "RISC". It seems very tightly coupled to the particular processor pipeline being proposed: It has dynamic typing (each register has a tag telling you what type of data it currently holds). Scalar, vector, FP, binary/decimial FP, etc. It has a set of "Queue" registers, which appear to be similar to Stack architectures or the Mill's "Belt" architecture (operands are read in the order they were written). Seems to think it can get away without needing branch prediction. It uses multi-threading for fine-grain task switching. It does this by copying all register writebacks to a 4kB region of memory so it's already performed the context before it's required.