3 ms·

Sorry to disappoint, AllSeeingEyes. What I taped out is a fairly modest instantiation of BOOM. I was trying to reduce risk and we had a very small area to play

Sorry to disappoint, AllSeeingEyes. What I taped out is a fairly modest instantiation of BOOM. I was trying to reduce risk and we had a very small area to play with, so I settled for ~4 CM/MHz. One potential win here would have been to use my TAGE-based predictor, which is an easy >20% IPC improvement on Coremark. Of course, a lot more reworking would be needed to achieve x86-64 clock frequencies.

microcolonel 9y ago
> which is an easy >20% IPC improvement on Coremark. Of course, a lot more reworking would be needed to achieve x86-64 clock frequencies. Maybe these should be expressed as Instructions Per Second (at peak and at the point of diminishing returns?) or something like that, rather than two independent numbers. Higher clock frequency actually seems like a bad thing, all else being equal. It seems to me that throughput ought to trend toward infinity, clock frequency toward zero. ;- )
- _chris_ 9y ago
  Of course it's important to always keep the "Iron Law" in mind, but it's far easier to compare ideas and talk about things in terms of IPC. For example, if a switch out one branch predictor for another, we're talking about an algorithmic change (implemented in hw) that will have an effect on IPC, and no effect on clock period (assuming we didn't screw something up). This is particularly useful when talking about a processor design, and not a specific processor in particular. As you said, there's a lot of good about slower clock frequencies, so you'll see the same ARM design being deployed at a variety of frequencies. Far easier to talk separately about a design's IPC from its achievable clock frequency (although both are important!).
AllSeeingEye 9y ago
No worries, Chris, I didn't expect entirely new processor design to play in Intel league :) Really hoping to get my hands on RISC-V-based SBCs next year.
- _chris_ 9y ago
  Me too!

microcolonel 9y ago

> which is an easy >20% IPC improvement on Coremark. Of course, a lot more reworking would be needed to achieve x86-64 clock frequencies. Maybe these should be expressed as Instructions Per Second (at peak and at the point of diminishing returns?) or something like that, rather than two independent numbers. Higher clock frequency actually seems like a bad thing, all else being equal. It seems to me that throughput ought to trend toward infinity, clock frequency toward zero. ;- )

_chris_ 9y ago
Of course it's important to always keep the "Iron Law" in mind, but it's far easier to compare ideas and talk about things in terms of IPC. For example, if a switch out one branch predictor for another, we're talking about an algorithmic change (implemented in hw) that will have an effect on IPC, and no effect on clock period (assuming we didn't screw something up). This is particularly useful when talking about a processor design, and not a specific processor in particular. As you said, there's a lot of good about slower clock frequencies, so you'll see the same ARM design being deployed at a variety of frequencies. Far easier to talk separately about a design's IPC from its achievable clock frequency (although both are important!).

AllSeeingEye 9y ago

No worries, Chris, I didn't expect entirely new processor design to play in Intel league :) Really hoping to get my hands on RISC-V-based SBCs next year.

_chris_ 9y ago
Me too!