I myself have had little difficulty in debugging Chisel designs using waveforms: virtually every Chisel node has its name maintained in Verilog. Sure, there ar

I myself have had little difficulty in debugging Chisel designs using waveforms: virtually every Chisel node has its name maintained in Verilog. Sure, there are many, many more temporary variables created between nodes, but what I care about when debugging is "what are the values of my Chisel nodes"? It's like debugging by looking at assembly, but with your C/C++ variable names carried through to the disassembly.