3 ms·
As a RISC-V core implementer, I'm super interested in answers to this question. Some of the things I've pondered is ways to figure out 1) what branch am I const
by _chris_ 9y ago
As a RISC-V core implementer, I'm super interested in answers to this question. Some of the things I've pondered is ways to figure out 1) what branch am I constantly mispredicting and 2) what load is constantly cache-missing. Not sure the best way to expose that to the programmer, particularly in a way that's cheap for most cores.
- strstr 9y ago1) Modern LBR might solve this. LWN has a summary (though I've only skimmed this): https://lwn.net/Articles/680996/ https://lwn.net/Articles/680996/ 2) Not sure for this, though I can think of some crappy hacks: --A) Timed LBR mentioned in that LWN article (somewhat indirect, but might get the job done) --B) use perf counter overflow interrupts (for cache misses) and set the perf counter initial value high (which should let you sample the cache miss locations). This can only tell you if a particular load is making up a large fraction of your overall cache misses (which is probably not super useful). Edit: Forgot about PEBS, which is really what you want for 2).