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Intel forges ahead to 10nm, will move away from silicon at 7nm
- wyager 12y agoDo they know what they're going to move to?
- TaylorAlexander 12y ago"More interesting than 10nm, though, is the news that Intel is looking to move away from silicon FinFETs for its 7nm process. While Intel didn't provide any specifics, we strongly suspect that we're looking at the arrival of transistors based on III-V semiconductors. III-V semiconductors have higher electron mobility than silicon, which means that they can be fashioned into smaller and faster (as in higher switching speed) transistors."
- sliverstorm 12y agoTo those unfamiliar with "III-V": Think GaAs (Gallium Arsenide) and friends. gallium arsenide (GaAs) has six times higher electron mobility than silicon, which allows faster operation... Conversely, silicon is robust, cheap, and easy to process, whereas GaAs is brittle and expensive, and insulation layers can not be created by just growing an oxide layer; GaAs is therefore used only where silicon is not sufficient. -- Wikipedia
- eclipxe 12y agoGallium Arsenide Valley doesn't have quite the same ring to it does it...
- sliverstorm 12y agoBetter than "Gaas Valley", at least.
- 1123581321 12y agoHow abou Gall Arse Valley?
- anonbanker 12y agotake this as an omen of the global shelf-life of SV.
- lmm 12y agoI think it's just the extra word. "Gallium Valley" sounds pretty cool, and "Arsenide Valley" sounds like a Bob Dylan song.
- higherpurpose 12y agoThat doesn't sound like good news for Intel chip prices.
- hga 12y agoIn many way's Moore's Law has been a law of economics. Look at the charts in the article; Intel will at least intend to continue the drop in cost per transistor, even if the price of a mm^2 of wafer continues to go up.
- kolanos 12y agoWill Intel be producing its own III-Vs or will it be sourcing it from somewhere else? Who are the major producers of III-Vs?
- quarterwave 12y agoCrystalline III-V channels can be grown epitaxially on silicon substrates, with buffer layers to grade the strain due to crystal lattice mismatch. With silicon wafers heading to 450mm diameter the economics would argue against native III-V substrates. One advantage of native III-V substrates is they are semi-insulating (very high resistivity) so there is no need for transistor isolation wells. However, insulated substrates could be obtained on silicon by means of wafer bonding with an intermediate dielectric layer.
- skaevola 12y agoAs they say: "Gallium Arsenide is the material of the future, and will always remain so" (1986)
- deleted 12y ago[deleted]
- gwern 12y agoThat's vague. I hope it's just Intel being quiet... I was under the impression that cutting-edge chips requires deep experience and planning - Intel must know exactly what they're going to move to if they're going to have any prayer of coming out with chips on a timely basis after 10nm in 2017.
- NamTaf 12y agoIt surely has to be. The jump from silicon at a mass scale is going to have an incredibly high barrier to entry so I can only see the most entrenched players making it. It seems to me a prime opportunity for the big players to entrench their {mon|du}opoly over the industry. I know I'd be keeping specifics as tightly controlled as possible until the last moment. It's one of those rare big jumps that really separate the players in the field.
- tedsanders 12y agoThe fact is that no one knows, not even Intel. Many hoped-for technologies have failed to pan out before. For example, the industry had placed high hopes on EUV lithography (in 2007 they hoped it would be ready by 2010), but continued problems make that technology look less and less likely today, at least for the short-term. III-V semiconductors are another major hope for the industry (a hope that's been around for decades), but now delays have pushed that from 10 nm to 7 nm. Imec has been working for over 10 years on a way of growing III-V semiconductors in tiny trenches to make it cheap enough, but until they actually ship product, no one knows if it's good enough to work. It's a scary time for the industry, as Moore's law comes to an end. (All that said, even if no one knows for sure what's coming next, that doesn't mean nothing will. The semiconductor industry is throwing billions of dollars and thousands of engineers at many potential solutions in parallel. Even if plan A falls through, there is always a heavily researched plan B, C, and D.)
- leoc 12y agoIs this description of the difficulties of EUV lithography http://semiaccurate.com/2013/02/13/euv-moves-forward-two-steps-back-one/ http://semiaccurate.com/2013/02/13/euv-moves-forward-two-ste... fairly accurate or not? It's certainly very funny. I also note that Seymour Cray wanted to do gallium arsenide CPUs back in the late '80s: https://www.youtube.com/watch?v=xW7j2ipE2Ck https://www.youtube.com/watch?v=xW7j2ipE2Ck .
- bsder 12y agoNo. Moore's law is stopping hard. No material represents a real advantage over silicon. Static RAM cells haven't scaled for about two generations now, but you could still scale functional transistors. Now, even that is stopping. Moore's Law was more an economic law than a physical one. Exponential growth has to run out sometime.
- dbrian 12y ago>Moore's law is stopping hard. I don't know.. people said the same thing when clock rates got close to 4Ghz. We always seem to find ways to work around physical limits.
- seanmcdirmid 12y agoWe fixed that problem by dropping back to under 2GHz; focusing on clock rate rather than IPC and energy efficiency was just a stupid time for Intel and the industry.
- bane 12y agoIt was a classic case of the marketing department taking over the farm.
- bsder 12y agoWell, that was the beginning of the breakage. Things actually broke at 90nm. Gate leakage went up enough that most analog/RF circuits scaled their transistors back up to 130-150nm dimensions while the digital guys cashed in the density increase one last time. 65nm was the first node where static RAM cells didn't scale with the rest of the digital circuitry. RAM cells are more sensitive to leakage since they have a "writability constraint" where you have to be able to shove enough electrons from outside the cell, through a transistor, with enough oomph to change the state inside the RAM cell. 40nm was where RAM scaling really broke. Designers had to start jumping through amazing hoops to support tricks for the manufacturing guys to eke out the last jump even for standard digital circuits. Most technologies started trading off multiple gate oxide thicknesses to manage leakage current. 28nm was where everything basically went to hell. The strong form of Moore's Law (twice the transistors for same cost) broke. RAM cells are way off the scaling curve. Leakage is everywhere. Multiple gate oxide thicknesses are the rule, not the exception. Designers are jumping through tremendous hoops for manufacturing (aligning all gates in the same direction over the entire chip, for example). Below 28nm has been a disaster, and, as pointed out, a lot of the sub-28nm stuff is more marketing than actual physical dimensions.
- mverwijs 12y agoIf you're into that sort of thing, the SPIE conference in San Jose (this week) is the place to be. And the people to follow. http://spie.org/AL/conferencedetails/alternative-lithographic-technologies#2086090 http://spie.org/AL/conferencedetails/alternative-lithographi...
- ChuckMcM 12y agoMakes me sad I'm not going to ISSSC. There is an interesting debate about feature size though. Devices on silicon for a long long time were essentially 2D, patterns on the top surface of Silicon. "Feature size" in this environment directly translated into area which directly translated into the die size. As features got smaller you started getting 'trench fets' and other tricks to increase the effective size of the gates so that leakage current wasn't insane. So at what point then do the circuit elements become fully vertical, which is to say that viewed from the 'top' the transistor is 10 nm on a side but vertically its 22 nm 'tall' ? And other tricks where the silicon layers are separately tested and 'thinned' and then packaged as a sandwich for final testing with ion implanters creating the vias between the connecting layers. Really interesting work in that sort of stuff going on.
- wcoenen 12y agoFor comparison, bond lengths are on the order of 0.2 nm. https://en.wikipedia.org/wiki/Bond_length https://en.wikipedia.org/wiki/Bond_length The lattice constant of unstrained silicon is 0.543 nm.
- deleted 12y ago[deleted]
- TheLoneWolfling 12y agoSo ~18-19 atoms across, then?
- toufka 12y agoI asked about this yesterday [1], and I found this article[2]. I can't speak to the validity, but it appears that the 'distances' used in these marketing concepts are not the same distances that are used to measure things. I'm still curious what the actual controllable resolution of the feature sizes are in the '7nm process'. I get the feeling that it's more like 30nm, but the effective feature density is greater than yesterday because there is more control vertically, and diagonally, etc. and so they need a smaller number than yesterday. But still just ~30nm (not actually 7nm). [1] https://news.ycombinator.com/item?id=9092506 https://news.ycombinator.com/item?id=9092506 [2] http://spectrum.ieee.org/semiconductors/devices/the-status-of-moores-law-its-complicated http://spectrum.ieee.org/semiconductors/devices/the-status-o...
- nhaehnle 12y agoWhen Intel say they have 52nm wire pitch, this means that they produce wires that are 26nm wide, with 26nm distance between wires. Producing wires that are thinner, or that are closer together, is unreliable. That said, they are probably able to position those wires at a higher precision. Without being involved in the manufacturing myself, I deduce this mainly from looking at optical proximity correction[1], for example, it's clear that the final masks used for production have more detail. Another indication is the fact that different masks seem to be aligned to basically nm-level precision (otherwise, the different parts of transistors and the vertical interconnects (vias) between wiring planes would not match up properly). The photographs one sees of the final product also indicate this. This means that the location of wires could theoretically be controlled very precisely, but for a mixture of wavelength and other (chemical? surface tension?) reasons, the size of the wires cannot be made smaller reliably. I'd be curious to know how precise this alignment really is, and I've never seen numbers for it, but it must be incredibly precise. Given that a large part of it can be done optically, this is not even that surprising, compared to some of the other magic that's going on here. [1] http://en.wikipedia.org/wiki/Optical_proximity_correction http://en.wikipedia.org/wiki/Optical_proximity_correction
- spunwasi 12y agoWitchcraft!
- stcredzero 12y agoGallium Arsenide? If that's true, then it will be like a sign of the apocalypse. The old saw has been: "Gallium Arsenide: Technology of the Future! Always was. Always will be!"
- bsdpython 12y agoMoore first made his claim in 1965. Assuming we have at least 5 more years wringing out efficiencies with the move to 10nm that's 55 years of continuous innovation. It's mind boggling. Maybe there will be a gap until the next major breakthrough but an entirely new process will come along eventually.
- higherpurpose 12y agoMy guess is we'll probably need something like graphene. Gallium Arsenide seems more like a 10 year stop-gap than a 50 year revolution. The problem is we can't get any "smaller", because we enter the quantum world and that's something entirely different. However, with graphene we can keep the transistors the same, but raise the clock speeds each generation, perhaps up to 1 TeraHerz or more, with a Moore's Law-like rate of improvement in performance.
- IanCal 12y agoThere's still a big problem with just upping the speed. If we have a chip running at 1THz then in each clock cycle light can only travel 3mm. Moving to more complex 3d chips could help improve performance, but there are limits to the number of dimensions we have too.
- eloff 12y agoYeah, I don't think 1 THz is achievable, but we can likely do substantially better than 4 Ghz, even when we can't go smaller. Then there are also gains to be made from building bigger, building in 3 dimensions, decreasing waste heat, etc. I suspect that innovation with chips will get bumpier, but likely overall maintain the pace of innovation for a couple decades more - which is all we need to get into really interesting territory re AI and other things.
- tormeh 12y agoYeah, transistor size might reach their top pretty soon, but with 3D circuits and new materials speeds will continue to increase. I would bet that improvements will become less predictable, though. Unfortunately, investors really dislike unpredictability, so R&D spending will probably drop.
- manigandham 12y agoIf anyone is interested in the manufacturing of these chips, this is an old but fascinating video: https://www.youtube.com/watch?v=NGFhc8R_uO4 https://www.youtube.com/watch?v=NGFhc8R_uO4
- chii 12y agowow, that was super interesting.
- pierre 12y agoThanks! It was really instructive.
- deleted 12y ago[deleted]
- rwmj 12y agoAnd here's a video from the 1970s, probably the first and last time Intel let anyone inside one of their fabs with a camera: https://www.youtube.com/watch?v=HW5Fvk8FNOQ https://www.youtube.com/watch?v=HW5Fvk8FNOQ
- TazeTSchnitzel 12y ago26 minutes in, and this may be the best documentary on the then-future use of computers I've seen.
- dcsommer 12y agoAs someone nearly irrationally annoyed by the collective inefficiency of all the Javascript being run in the world, I kind of wish the computational "free lunch" ends sooner than later so the frontend world has to move towards the zero-cost abstractions and techniques being adopted server side. Too bad these hardware engineers are really good at their jobs!
- asdkl234890 12y agoOn the other hand John Carmack isn't exactly known for his inefficient code, and yet he's still pushing the limits of hardware.
- ajuc 12y agoLast I've checked java and .net were the most popular server-side languages, and they are all about costly abstractions. Dependency injection, reflection, AbstractFactoryBuilderManagerBean etc. In fact I've yet to see java server-side stacktrace that's less than 100 lines long. Usually it's more like 1000 lines, with a few RMIs inside. On the other hand, the js stacktraces I've seen (mostly hobby projects, so I may be biased) are usually less than 50 lines, often just 10 or so. Not good, but much better.
- lmm 12y agoIf you compare java projects from the same era as the js projects you'll see similarity; modern java frameworks are a lot more lightweight.
- sireat 12y agoI keep reading how 22nm, 20nm, 16nm, 14nm and so on are not true measurements anymore but mostly marketing speak. This is true of all fab companies. That is the move from 22nm to 14nm did not give you double the transistor count from the same area die. So has anyone done a comparison of transistor count on the same size die over the years depending on the process?
- marcosdumay 12y agoFeture size never had a completely linear relation to transistor density. Recently that non-linearity is just becomming worse.