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The hardware description languages (HDL) used in chip development are like programming languages. The existing models understand them and can do a lot with them

The hardware description languages (HDL) used in chip development are like programming languages. The existing models understand them and can do a lot with them. You don’t need to have separate, specialty models designed for this work to use LLMs in chip design workflows. Design verification also involves a lot of traditional programming which benefits from LLMs. So it’s not meaningless at all. You could download some of the open source chip design software today and the LLMs could even help you get started on your own tiny chip if you are so interested.

ses1984 4mo ago
The question isn’t whether or not they employed a particular tool, the question is how big of an impact did it have.
- deleted 4mo ago
  [deleted]
IshKebab 4mo ago
> The existing models understand them and can do a lot with them. In my experience they are not especially good at SystemVerilog. There's a lot of knowledge about it that is locked behind paywalls and it's very niche. My guess is the "from scratch" here is quite the exaggeration. Otherwise why did they need Broadcom?
- whynotminot 4mo ago
  Doesn’t Broadcom bring a lot more to bear here than just Verilog? Including relationships with the actual fabricators.
  - IshKebab 4mo ago
    I doubt that is really significant - fabs are happy to work with anybody. What they will likely bring is: * Physical design team (stupidly known as the "backend"). This is extremely specialised knowledge and most chip companies don't really want to have to deal with it if they can avoid it. * IP blocks. Especially for annoying things like phys, memory controllers, USB controllers, PLLs, power, etc. These things are difficult to do, difficult to test, and often critical (good luck if your clock doesn't work...) I would not at all be surprised if Broadcom supplied CPUs too. My total guess at what happened is Broadcom supplied most of a SoC and OpenAI added an LLM coprocessor module to it, and probably asked them to add like 10x more DRAM interfaces.
- aseipp 4mo ago
  Not having a free toolchain that can actually handle the real language has probably been pretty bad on the downstream public knowledgebase. Hopefully Verilator can eventually close that hole, and there can be more high-quality designs and codebases incorporated into future models. Claude is at least good enough to write SV that triggered a compiler crash or two. :)
- deleted 4mo ago
  [deleted]
- cloudengineer94 4mo ago
  Broadcom also has direct allocation with TSMC, which is a big win
knicholes 4mo ago
I tried making a button using Claude entirely (including the 3D printed enclosure) and it effed up pretty hard with the traces and the header spacing. The project was a big red arcade button that plays the "ah-my-groin.mp3" when pushed (from Simpsons). It did cool work on saving battery life, and the 3d enclosure was awesome, but yeah, I'm convinced I'd have to do another version or two of the custom chip until it came back right. I used a Blender MCP for the 3d modeling. I used a KiCAD MCP server for the chip design/validation. I think we're not there yet. I've been meaning to look at this flux.ai to see if it has the prompts/workflow worked out better than what I was able to cobble together in a few hours. Maybe Alteryx's MCP server would have been better. I'll try that this weekend for another board I've got.
- Aurornis 4mo ago
  > I tried making a button using Claude entirely (including the 3D printed enclosure) and it effed up pretty hard with the traces and the header spacing. PCB design and 3D CAD design are different topics. Hardware Description Languages are closer to programming languages than CAD. Look at some Verilog to get an idea - https://en.wikipedia.org/wiki/Verilog https://en.wikipedia.org/wiki/Verilog
  - knicholes 4mo ago
    Right. KiCAD for PCB design. Blender for 3D CAD. Oh, are you saying I should have used something other than the KiCAD MCP server for better results?
    - dcrazy 4mo ago
      They’re saying that VHDL is an entirely different concept than physical modeling.
    - giancarlostoro 4mo ago
      You're comparing apples and oranges.
    - quadrature 4mo ago
nradov 4mo ago
Most HDL code is locked up behind corporate firewalls and not available as training data. While LLMs can handle it to an extent there's a lot of room for improvement. I'll bet that OpenAI and their competitors are racing to license this IP from major hardware vendors in order to compete in the chip design vertical.
- tonfa 4mo ago
  Does it work better when using compiler based ecosystem (e.g. https://github.com/llvm/circt https://github.com/llvm/circt)
- bsder 4mo ago
  There is quite a lot of Verilog/SystemVerilog and VHDL code in the wild. And hardware description language code is very simple and straightforward relative to programming code. And the two things that take up VAST amounts of time in ASIC design are testbenches and timing closure. A LOT of hardware design is testbenches to verify things. AI is REALLY GOOD at generating things like testbenches. And nobody really cares if the quality of your testbench code sucks as long as it validates what it claims to. I don't know how good AI is at timing closure, but I wouldn't necessarily be surprised if it is pretty good at it up to the physical point. That's lots of textual output which you can put a constraint on. Everything involving physical design, though, tends to be a disaster waiting to happen if you let AI loose on it.
doxeddaily 4mo ago
This reminds me of the dude on youtube building a chip fab in his shed.
holoduke 4mo ago
One day we can design our own pcb with chips, hardware and other io. Companies will accept these as files and you can collect your pcb the same day. I think in China they are doing this already
- remexre 4mo ago
  hasn't pcbway been doing this for years?
einpoklum 4mo ago
> The existing models understand them No they don't.

ses1984 4mo ago

The question isn’t whether or not they employed a particular tool, the question is how big of an impact did it have.

deleted 4mo ago
[deleted]

IshKebab 4mo ago

> The existing models understand them and can do a lot with them. In my experience they are not especially good at SystemVerilog. There's a lot of knowledge about it that is locked behind paywalls and it's very niche. My guess is the "from scratch" here is quite the exaggeration. Otherwise why did they need Broadcom?

whynotminot 4mo ago
Doesn’t Broadcom bring a lot more to bear here than just Verilog? Including relationships with the actual fabricators.
- IshKebab 4mo ago
  I doubt that is really significant - fabs are happy to work with anybody. What they will likely bring is: * Physical design team (stupidly known as the "backend"). This is extremely specialised knowledge and most chip companies don't really want to have to deal with it if they can avoid it. * IP blocks. Especially for annoying things like phys, memory controllers, USB controllers, PLLs, power, etc. These things are difficult to do, difficult to test, and often critical (good luck if your clock doesn't work...) I would not at all be surprised if Broadcom supplied CPUs too. My total guess at what happened is Broadcom supplied most of a SoC and OpenAI added an LLM coprocessor module to it, and probably asked them to add like 10x more DRAM interfaces.
aseipp 4mo ago
Not having a free toolchain that can actually handle the real language has probably been pretty bad on the downstream public knowledgebase. Hopefully Verilator can eventually close that hole, and there can be more high-quality designs and codebases incorporated into future models. Claude is at least good enough to write SV that triggered a compiler crash or two. :)
deleted 4mo ago
[deleted]
cloudengineer94 4mo ago
Broadcom also has direct allocation with TSMC, which is a big win

knicholes 4mo ago

I tried making a button using Claude entirely (including the 3D printed enclosure) and it effed up pretty hard with the traces and the header spacing. The project was a big red arcade button that plays the "ah-my-groin.mp3" when pushed (from Simpsons). It did cool work on saving battery life, and the 3d enclosure was awesome, but yeah, I'm convinced I'd have to do another version or two of the custom chip until it came back right. I used a Blender MCP for the 3d modeling. I used a KiCAD MCP server for the chip design/validation. I think we're not there yet. I've been meaning to look at this flux.ai to see if it has the prompts/workflow worked out better than what I was able to cobble together in a few hours. Maybe Alteryx's MCP server would have been better. I'll try that this weekend for another board I've got.

Aurornis 4mo ago
> I tried making a button using Claude entirely (including the 3D printed enclosure) and it effed up pretty hard with the traces and the header spacing. PCB design and 3D CAD design are different topics. Hardware Description Languages are closer to programming languages than CAD. Look at some Verilog to get an idea - https://en.wikipedia.org/wiki/Verilog https://en.wikipedia.org/wiki/Verilog
- knicholes 4mo ago
  Right. KiCAD for PCB design. Blender for 3D CAD. Oh, are you saying I should have used something other than the KiCAD MCP server for better results?
  - dcrazy 4mo ago
    They’re saying that VHDL is an entirely different concept than physical modeling.
  - giancarlostoro 4mo ago
    You're comparing apples and oranges.
  - quadrature 4mo ago

nradov 4mo ago

Most HDL code is locked up behind corporate firewalls and not available as training data. While LLMs can handle it to an extent there's a lot of room for improvement. I'll bet that OpenAI and their competitors are racing to license this IP from major hardware vendors in order to compete in the chip design vertical.

tonfa 4mo ago
Does it work better when using compiler based ecosystem (e.g. https://github.com/llvm/circt https://github.com/llvm/circt)
bsder 4mo ago
There is quite a lot of Verilog/SystemVerilog and VHDL code in the wild. And hardware description language code is very simple and straightforward relative to programming code. And the two things that take up VAST amounts of time in ASIC design are testbenches and timing closure. A LOT of hardware design is testbenches to verify things. AI is REALLY GOOD at generating things like testbenches. And nobody really cares if the quality of your testbench code sucks as long as it validates what it claims to. I don't know how good AI is at timing closure, but I wouldn't necessarily be surprised if it is pretty good at it up to the physical point. That's lots of textual output which you can put a constraint on. Everything involving physical design, though, tends to be a disaster waiting to happen if you let AI loose on it.

doxeddaily 4mo ago

This reminds me of the dude on youtube building a chip fab in his shed.

holoduke 4mo ago

One day we can design our own pcb with chips, hardware and other io. Companies will accept these as files and you can collect your pcb the same day. I think in China they are doing this already

remexre 4mo ago
hasn't pcbway been doing this for years?

einpoklum 4mo ago

> The existing models understand them No they don't.