5 ms·
Converting an Integer to a Decimal String in Under Two Nanoseconds
- jqpabc123 5mo agoOur design exploits the AVX-512 instruction set AVX-512 is being discontinued in newer Intel consumer CPUs, particularly with the Alder Lake series, where it has been completely disabled through BIOS updates.
- anematode 5mo agoTo the contrary, Nova Lake, coming out this year, will have it.
- yvdriess 5mo agoAnd that's a shame, but the relevant workloads typically run on server class CPUs.
- adrian_b 5mo agoFrom all the workloads that I execute on my laptops or desktops, there is only one where the speed matters yet it is not significantly affected by the use of the AVX-512 ISA: the compilation of big software projects. All the other things that I do and which can take a noticeable CPU time (i.e. not time used for waiting on SSDs or other peripherals) can be accelerated by AVX-512. This includes things like computing file hashes, data compression and encryption algorithms, graphics/audio/video algorithms and also EDA/CAD applications.
- adrian_b 5mo agoYour comment is obsolete. AVX-512 had been discontinued in the CPU generations from Alder Lake until the Panther Lake, Wildcat Lake and Clearwater Forest CPUs introduced during the first half of 2026, but Intel has committed than all future Intel CPUs will implement the complete 512-bit variant of the AVX-512 a.k.a. AVX10 ISA, starting with the Nova Lake desktop and laptop CPUs, to be launched by the end of this year. Obviously, the competition from the AMD Zen 4, Zen 5 and Zen 6 CPUs, all of which implement AVX-512 and easily beat any Intel CPU in any workload that has been updated to use the AVX-512 ISA, has forced Intel to reconsider its previous decision.
- xlii 5mo agoI wonder if this can be categorized as galactic algorithm. I can't imagine systems where bulk of processing goes into integer to decimal string conversion but maybe there are such. https://en.wikipedia.org/wiki/Galactic_algorithm https://en.wikipedia.org/wiki/Galactic_algorithm
- oersted 5mo agoMy understanding of a Galactic Algorithm is that it has better performance scaling based on input size/complexity, but its overhead is such that it will not actually be faster unless you use it for impracticality large inputs. I don’t think it has much to do with the case of an algorithm that offers a faster solution to a problem that is rarely a bottleneck (not sure if that’s true in this case anyway).
- adrian_b 5mo agoI always use binary interchange formats between programs so I am not familiar with the overhead caused by format conversions. Even when displaying numbers for reading them, in the case of floating-point numbers that are displayed in the "scientific" format, i.e. with exponents, I prefer to have only the exponent as a decimal number, but the significand as a hexadecimal number. So I do not need fast algorithms for number conversions. Nonetheless, there are plenty of people who advocate the use of JSON, XML and similar formats, in which case I assume that number conversions can take a non-negligible time, which might be decreased by such fast algorithms.
- superjan 5mo agoYou know, if can change code without overhead to ends of the pipeline, using the language & library of my choice, I’d do this too. For many of us this isn’t always the case.
- Tuna-Fish 5mo agoIt takes a substantial amount of time when emitting lots of numbers in JSON, happens very commonly. And this algorithm has low constant costs, and does not take dramatically more icache than the simple versions. There is no reason not to use this if your compile target can handle avx-512.
- IshKebab 5mo agoVery impressive! But yeah AVX-512 is an awkward requirement.
- adrian_b 5mo agoThere already exists a large installed base of AMD Zen 4 and Zen 5 CPUs. Next year, these AVX-512 supporting CPUs will be joined by AMD Zen 6 and Intel Nova Lake. Starting with Intel Nova Lake, all future Intel CPUs will support AVX-512.
- IshKebab 5mo agoSure, it's not just the support though. As I understand it it also has serious power and frequency implications. Also if your process uses AVX-512 you suddenly have an extra 2kB of data to save/restore on context switches. Maybe not super significant but I really doubt this will ever make it into standard libraries.
- adrian_b 5mo agoAVX-512 increases energy efficiency and performance unconditionally, in all AMD Zen 4 and later CPUs and in all Intel Ice Lake and later CPUs. Only in the now obsolete Intel server and workstation CPUs from the Skylake Server, Cascade Lake and Cooper Lake families, using AVX-512 was a win when a great number of vector instructions were executed, but it was a loss when only a small number of vector instructions were executed. This was caused by a really stupid Intel voltage and frequency controller, which could not react quickly enough to changes in power consumption. Because of this, it dropped preemptively the clock frequency, before there was any need for this, for fear that the CPU will overheat if the power consumption will increase in the future and the voltage/frequency controller will not be able to decrease it fast enough, before reaching the temperature limit. For the same reason, the clock frequency was kept low a very long time after the last vector instruction seen. Now this is pretty much history, because few have kept those 7 to 10 years old inefficient servers and those who have kept them normally run workloads that either use a lot of vector instructions or they do not use such instructions. Nowadays the only reason for not using AVX-512 is when the software is intended to be widely used and one does not want to distribute 2 versions, one with AVX-512 for AMD or P-core Intel CPUs and one with AVX for E-core or hybrid Intel CPUs or very old AMD CPUs.
- Cold_Miserable 5mo agoThis is just a worse copy of the original ifma method. Sneller is even better for max throughput.
- Nnnes 5mo ago> Sneller is even better for max throughput. I see https://sneller.ai/blog/avx512-itoa/ https://sneller.ai/blog/avx512-itoa/, which reports ~0.75ns/number for <=7 bytes (compared to ~1ns/n for Champagne-Lemire, I would assume on 3 year newer hardware), but ~2.6ns/number for >=8 bytes (vs ~1.3ns/n for Champagne-Lemire). Perhaps it has improved in the 3 years since the blog post was written? Their main GitHub repository is no longer public, so I don't see a good way to test it myself.
- Nokinside 5mo agoSounds familiar. If one of the authors Lemire? Of course. SIMD-accelerated integer-to-string conversion https://lemire.me/blog/2026/05/18/simd-accelerated-integer-to-string-conversion/ https://lemire.me/blog/2026/05/18/simd-accelerated-integer-t... Other speedy things: On-Demand JSON: A Better Way to Parse Documents? https://lemire.me/en/publication/arxiv231217149/ https://lemire.me/en/publication/arxiv231217149/ Parsing Millions of URLs per Second https://lemire.me/en/publication/arxiv231110533/ https://lemire.me/en/publication/arxiv231110533/ Transcoding Unicode Characters with AVX-512 Instructions https://lemire.me/en/publication/arxiv221205098/ https://lemire.me/en/publication/arxiv221205098/
- vitaminCPP 5mo agoHehe it's always Lemire !
- childintime 5mo agoWhat will be the lifetime of AVX512? There have been many similar extensions before it. So it's a great result, but heavily marked by the target platform. I have the hope that RISC-V vector extensions will prove to be the more durable substrate to develop on, and a result there would be much more relevant for the future.
- simonask 5mo agoIt will be literal decades before RISC-V becomes mainstream. Not because it’s not a perfectly fine ISA, but because business incentive structures aren’t nowhere near supporting it. Literal man-millennia have been poured into writing software for both x86 and ARM, and nobody seems close to designing a competitive RISC-V chip.
- adrian_b 5mo agoAVX-512, originally called the "Larrabee New Instructions" has been the only decent vector extension of the Intel-AMD ISA, which has been coherently planned instead of being a heap of more or less randomly chosen instructions, each being thought to be useful to accelerate some particular benchmark or a certain workload of one of the big customers. MMX (Pentium MMX, 1997) sucked badly (because in designing it ease of implementation was prioritized over usefulness), SSE (Pentium III, 1999) was much worse than the simultaneously launched Motorola AltiVec, and AVX (Sandy Bridge, 2011) was much worse than the simultaneously developed Larrabee New Instructions (despite the fact that Sandy Bridge was developed by the A-team, while Larrabee was developed by the C- or D-team, which however had hired competent consultants from outside Intel, experienced in programming games and graphic applications). AVX-512 is for now better than any competitive vector ISA, both in the achievable energy efficiency and in the achievable performance. Obviously, it is possible that some future Aarch64 (Arm) or even RISC-V CPUs will change this, by implementing wider registers and execution units and by adding any missing operations. The SME ISA extension (Scalable Matrix Extension), which is available in the latest Apple CPUs and in the current 2026 generation of Arm C1 CPUs, has the potential to be more efficient than AVX-512, exploiting the fact that the current Intel AMX ISA is intended only for ML/AI and not also for general-purpose computing. Nonetheless this may happen only in a rather distant future, because neither Apple nor Qualcomm nor Arm seem interested to make products suitable for the needs of technical and scientific computing, like Intel and AMD. Because of that, in the existing CPUs with SME the ratio between SME execution units and the general-purpose CPU cores is low, resulting in a low total throughput.
- amelius 5mo agoDecimal strings are for human consumption, I suppose. Not sure if the nanosecond timescale is relevant then (unless you send these numbers to billions of people which is unlikely). Sounds like a pointless exercise, or maybe they should have picked a better example.
- pipe2devnull 5mo agoWow that’s a bit harsh. You can’t think of any examples where you may need to send a string to something but want to do it quickly?
- amelius 5mo agoYeah maybe a bit harsh. But the point is if you are looking for that kind of performance, I don't see why you wouldn't send binary data and then unpack it as needed.
- appreciatorBus 5mo agoIf you control both ends of the pipe, then sure. But for better or worse, large chunks of infrastructure expect to send or receive JSON.