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TSMC unveils 1.6nm process technology with backside power delivery
- tvbv 3y agocould someone ELi5 the backside power delivery please ?
- bayindirh 3y agoSignal wires and power wires are not routed together, but separately. As a result, transistors are sandwiched between two wiring stacks. Resulting in lower noise, but makes heat removal a bit harder AFAICS. See the image at: https://www.custompc.com/wp-content/sites/custompc/2023/06/Intel-PowerVia-backside-power-delivery-03.jpg https://www.custompc.com/wp-content/sites/custompc/2023/06/I...
- Tempest1981 3y agoHow many power layers are there? Or how do the power "wires" cross over each other? Are they sparse, like wires? Or solid, like the ground plane of a PCB? Are there "burried vias"?
- gostsamo 3y agoAn article on the topic though about Intel: https://spectrum.ieee.org/backside-power-delivery https://spectrum.ieee.org/backside-power-delivery
- AnimalMuppet 3y agoSo, if I understood that correctly, "frontside" actually is the top side, and "backside" is actually the bottom side. They're delivering power from the bottom (substrate) side, and connecting the data on the top side.
- Keyframe 3y agoinstead of signals and power path going through the same side (frontside) causing all sorts of issues and inefficiency, they're decoupling where power is coming from (from the other, backside, err side). More importantly, intel saw it as one of two key technologies of them moving into angstrom era, and was touting itself they'll be the first one to bring it to life (not sure they did).. so this seems to be more of a business power move. more on all of it from anandtech: https://www.anandtech.com/show/18894/intel-details-powervia-tech-backside-power-on-schedule-for-2024 https://www.anandtech.com/show/18894/intel-details-powervia-...
- wwfn 3y agoI'm also clueless. First search brings up https://www.tomshardware.com/news/intel-details-powervia-backside-power-delivery-network https://www.tomshardware.com/news/intel-details-powervia-bac... with a nice diagram It looks like the topology for backside moves the transistors to the middle so "singal wires and power wires are decoupled and optimized separately" instead of "compete[ing] for the same resources at every metal layer"
- __s 3y agohttps://www.imec-int.com/en/articles/how-power-chips-backside https://www.imec-int.com/en/articles/how-power-chips-backsid... has some explanation that's a bit beyond ELI5, but they have 2 pictures: frontside: https://www.imec-int.com/_next/image?url=%2Fsites%2Fdefault%2Ffiles%2F2022-11%2Fimec%2520-%2520Figure%25201%2520-%2520Frontside%2520power%2520delivery.png&w=1280&q=75 https://www.imec-int.com/_next/image?url=%2Fsites%2Fdefault%... backside: https://www.imec-int.com/_next/image?url=%2Fsites%2Fdefault%2Ffiles%2F2022-11%2Fimec%2520-%2520Figure%25202%2520-%2520Backside%2520power%2520delivery%2520-%2520concept.png&w=1280&q=75 https://www.imec-int.com/_next/image?url=%2Fsites%2Fdefault%... Another graphic samsung used: https://www.thelec.net/news/photo/202210/4238_4577_1152.jpg https://www.thelec.net/news/photo/202210/4238_4577_1152.jpg From https://www.tomshardware.com/pc-components/cpus/samsung-to-introduce-backside-power-delivery-to-2nm-class-production-node-report https://www.tomshardware.com/pc-components/cpus/samsung-to-i... > Typically, backside power delivery enables thicker, lower-resistance wires, which can deliver more power to enable higher performance and save power. Samsung's paper noted a 9.2% reduction in wiring length, enhancing performance
- barfard 3y agothe pics go to 404
- __s 3y agothanks, I've fixed them btw, you appear to be shadow banned, probably on account of being downvoted for making short comments like "good" or "I don't get it" Short & simple responses may be adequate at times, but usually people will view it as not adding anything Perhaps reviewing guidelines https://news.ycombinator.com/newsguidelines.html https://news.ycombinator.com/newsguidelines.html will give an idea of the ideal being yearned for (granted, it's an ideal). In general, trying to enhance the conversation with relevant information/ideas. "your links are 404" was definitely relevant here
- gcanyon 3y agoHow can you tell someone is shadowbanned?
- vollbrecht 3y agothere is a good youtube video that explains it https://www.youtube.com/watch?v=hyZlQY2xmWQ https://www.youtube.com/watch?v=hyZlQY2xmWQ
- brohee 3y agoNot ELI5 but I found this 20mn video pretty informative https://www.youtube.com/watch?v=hyZlQY2xmWQ https://www.youtube.com/watch?v=hyZlQY2xmWQ
- brennanpeterson 3y agoHalf your wires deliver power, half deliver signal. So if you do both on the same side, you need twice the density of wires. If you split the delivery into two parts, you get double the density without needing to make things smaller.
- blagie 3y agoThis isn't quite right. Big wires (ideally entire planes) deliver power. Small wires deliver signal. Half and half isn't the right split, and you don't want to make power wires smaller. The very different requirements of the two is where a lot of the gains come in.
- mbajkowski 3y agoIt is going to get even a bit more interesting when you consider power gaters and virtual power supplies. Now the real power will be on the back side and the virtual power will be on the front side. Fun time for power analysis.
- brennanpeterson 3y agoTrue! I went a little far in the name of 'eli5'. I think it roughly holds that you gain about a factor of 1.5 in routing density by removing the power distribution, so you can relax some critical patterning. But I havent looked closely in a long time.
- blagie 3y agoOft-missed pedagogical point for working with five-year-olds: Precision is important. You'll notice every comment I made was as simple as I can make it, but /technically correct/. I did not oversimplify to where I changed facts. * It's okay if five-year-olds don't fully understand something. That builds exposure, and leaves a placeholder for future information and curiosity. * On the other hand, if you build out an array of misconceptions, those become very expensive to address later. To a large extent, the younger the child, the more comfortable they will be with being told things they don't understand. A baby doesn't care if you're reading them a book on trucks or a book on homeomorphic transformations; they're picking out the phonemes. A toddler will trust you as an adult, and won't understand 90% of the stuff they hear anyways. A five-year-old, you can still say a lot they won't understand and they'll be not just okay but happy. By maybe seven, lack-of-understanding will become frustrating, and in most cases, by eleven, it's gone. I could write a long essay on this stuff, and why it's so important to maintain that ability to be confused and half-understand, but I very intentionally leave placeholders when working with five-year-olds.
- brikym 3y ago[flagged]
- blagie 3y agoELI5: ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power: * Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better. * Big wires, if near signal wires, can interfere with them working optimally (called "capacitance"). * Capacitance can slow down signals on the fine signal wires. * Capacitance also increases power usage when ones become zeros and vice-versa on signal wires. * Big wires also take up a lot of space. * Putting them on the back of the wafer means that things can go faster and use less power, since you don't have big power wires near your fine signal wires. * Putting them in back leaves a lot more space for things in front. * Capacitance between power wires (which don't carry signal) actually helps deliver cleaner power too, which is a free bonus! This is hard to do, since it means somehow routing power through the wafer. That's why we didn't do this before. You need very tiny wires through very tiny holes in locations very precisely aligned on both sides. Aligning things on the scale of nanometers is very, very hard. How did I do?
- consp 3y ago[flagged]
- pmx 3y agoThanks this was a very useful summary for me!
- vintendo64 3y ago
- sylware 3y agoIt seems the actually impressive thing here is the 15-20% less power consumption at same n2 complexity/speed.
- 654wak654 3y agoSounds like a response to Intel's 18A process [0], which is also coming in 2026. [0] https://www.tomshardware.com/tech-industry/manufacturing/intel-18a-based-cpus-will-ramp-to-high-volume-in-2026 https://www.tomshardware.com/tech-industry/manufacturing/int...
- Alifatisk 3y agoThis is a response to something that’s coming in 2 years? Incredible how far ahead they are
- HarHarVeryFunny 3y agoIntel is the one trying to catch up to TSMC, not vice versa! The link you give doesn't have any details of Intel's 18A process, including no indication of it innovating in any way, as opposed to TSMC with their "backside power delivery" which is going to be critical for power-hungry SOTA AI chips.
- shookness 3y agoWhile you are correct that it is Intel trying to catch TSMC, you are wrong about the origin of backside power delivery. The idea originated at Intel sometime ago, but it would be very ironic if TSMC implements it before Intel...
- Havoc 3y ago>1.6nm Gotta love how we now have fractions of a near meaningless metric.
- s_dev 3y agoWhy is it meaningless?
- Havoc 3y agoIt stopped being an actual measure of size long ago. The nm is t Nanometer anything it’s just a vague marketing thing attempting some sort of measure of generations
- chmod775 3y agoBecause it's not measuring anything, except the tech generation. It conveys about as much information as "iPhone 14".
- gwervc 3y agoIt's at least more easily understandable (lower is newer) than the average tech product naming scheme, especially those by Microsoft.
- tommiegannert 3y agoThe problem is it sounds like something any engineer can understand without domain knowledge, but interpreting it that way is completely wrong. The worst kind of naming. Not just IKEA-style random names (and I say that as a Swede,) but reusing a standard, while not keeping to what the standard is normally used for, and what it previously meant even in this domain. N1.6 is much better for naming node processes. Or even TSMC16.
- bmicraft 3y agoNormally? That "standard" hasn't been used "normally" for 20 years now. Arguably the new way is normal in every sense of the word
- gtirloni 3y ago> This technology is tailored specifically for AI and HPC processors that tend to have both complex signal wiring and dense power delivery networks Uh?
- baybal2 3y ago[dead]
- mastax 3y agoPardon?
- mazurnification 3y agoThere are certain trade offs when designing process. TSMC researched with partners how AI and HPC (high performance computing) chips most likely will look like and adjusted process accordingly. In fact this is big deal as until recently the processes were more tailored toward mobile application (that is were trading some switching performance for lower power consumption). Look like we are back in 2000s when speed/density is again more important than power consumption.
- magicalhippo 3y agoI imagine it's because AI and HPC processors are typically utilized much more fully than your regular desktop processor. A typical desktop CPU is designed to execute very varied and branch-heavy code. As such they have a lot of cache and a lot of logic transistors sitting idle at any given time, either waiting for memory or because the code is adding not multiplying for example. You can see that in the die shots like this[1] for example. I imagine the caches are relatively regular and uniform and as such as less complex signal wiring, and idle transistors means lower power requirements. AI and HPC processors are more stream-oriented, and as such contain relatively small cachees and a lot of highly-utilized logic transistors. Compare the desktop CPU with the NVIDIA A100[2] for example. Thus you got both complex wiring, all those execution units needs to be able to very quickly access the register file, and due to the stream-oriented nature one can fully utilize most of the chip so a more complex power delivery network is required. edit: Power delivery tracks can affect signal tracks due to parasitic coupling if they're close enough, potentially causing signals to be misinterpreted by the recipient if power usage fluctuates which it will do during normal operation (if say an execution unit goes from being idle to working on an instruction, or vice versa). Thus it can be challenging to fit both power and signal tracks in close proximity. [1]: https://wccftech.com/amd-ryzen-5000-zen-3-vermeer-undressed-high-res-die-shots-close-ups-pictured-detailed/ https://wccftech.com/amd-ryzen-5000-zen-3-vermeer-undressed-... [2]: https://www.tomshardware.com/news/nvidia-ampere-A100-gpu-7nm https://www.tomshardware.com/news/nvidia-ampere-A100-gpu-7nm
- tgtweak 3y agoA16 in 2027 vs Intel's 18A in full swing by 2026 feels like a miss on TMSCs behalf. This looks like an open door for fabless companies to try Intel's foundry service.
- akmittal 3y agoIntel has made lots of big promises, they have yet to catch us to TSMC
- crowcroft 3y agoIntel hasn't got a great track record in recent history. Really hoping they can hit their timeline though.
- SilverBirch 3y agoThere are definitely going to be people taking a bet on the Intel foundry, but Intel has tried this before and it has worked badly.
- onepointsixC 3y agoSounds like an easy short for you then.
- SilverBirch 2y agoI worked for Intel at a point where it was clear they were going to miss every important technical milestone you could name. The stock stayed high through every bad piece of news and was only when Gelsinger bit the bullet and told the truth that the stock actually tumbled, and it still didn't tumble back to below the point they were when it was obvious they were in trouble. In fact it reached really good high points long after it was obvious they were in trouble. Shorting is for only the most incontrovertible frauds as far as I'm concerned.
- rcxdude 3y agoAgainst OP maybe. Going short or long also depends on knowing what the market thinks will happen.
- futureshock 3y agoComments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.
- Workaccount2 3y agoIntel has a 1.4nm process in the pipeline for ~2027. They just took delivery on their first high NA EUV machine in order to start working on it. Their gamble however is that they need to figure out DSA, a long storied technology that uses self-forming polymers to allow less light to sharply etch smaller features. If they figure out DSA, they will likely be ahead of TSMC. If not, it will just be more very expensive languishing.
- saganus 3y agoDo you know the name of the company that produces the EUV machine? is it ASML? It is my understanding that only ASML had cracked the EUV litography, but if there's another company out there, that would be an interesting development to watch.
- singhrac 3y agoIt’s ASML.
- Rinzler89 3y ago>It is my understanding that only ASML had cracked the EUV litography Ackshually, EUV was cracked by Sandia Labs research in the US, with EUV light sources built by Cymer in the US. ASML was the only one allowed to license the tech and integrate it into their steppers after they bough Cymer in 2013. Hence why US has veto rights to whom Dutch based ASML can sell their EUV steppers to, as in not to China, despite ow much ASML shareholders would like that extra Chinese money.
- m3kw9 3y agoSo much for physical limitations, it seems you can keep halving smaller till infinity.
- zzz999 3y ago[dead]
- ThinkBeat 3y agoI am not sure I understand backside in this instance and the illustration in the article didn't entirely help. In general, at least in older time, one side of the CPU has all the nice pins on it, and the motherboard has a pincushion that the pins match nicely. At the top of the CPU you put a HUGE heatsink on it and off you go. In this configuration the power delivery must be via the pincushion, through some of the pins. Intuitively that sounds to me like the power is coming in the backside? But given that it is a big deal I am missing something. Is the power fed from the "top" of the cpu where the heatsink would sit?
- sgalloway 3y agoHere's a very good youtube video on the subject of backside power delivery I watched a few days ago. https://youtu.be/hyZlQY2xmWQ?si=JuXtzRy0U0onEzoe https://youtu.be/hyZlQY2xmWQ?si=JuXtzRy0U0onEzoe
- gosub100 3y agoThe "Hollywood accounting" transistor density aside, I think a new metric needs to become mainstream: "wafers per machine per day" and "machines per year manufactured". Getting these machines built and online is more important than what one machine (that might be less than 6 per year) can do. The information, I'm sure, is buried in their papers, but I want to know what node processes are in products available now.
- drekipus 3y agoif people find the topic interesting, I recommend the book "Chip War" [1] It's a great read. very dense in narrative facts. [1] https://www.amazon.com.au/gp/aw/d/1398504122/ref=ox_sc_act_image_2?smid=ANEGB3WVEVKZB&psc=1 https://www.amazon.com.au/gp/aw/d/1398504122/ref=ox_sc_act_i...
- RecycledEle 3y agoI love that they're using the back side now. It reminds me of finally using the back of a PCB.
- bitwize 3y agoAvailable in Apple products this Christmas, everybody else's in the back half of the decade, maybe.