16 ms·
Intel shows 8 core 528 thread processor with silicon photonics
- tgtweak 3y agoJust a shout-out to the STH team (hey Patrick) who have been live blogging literally every presentation and announcement from hot chips. I've been reading up on next gen xeons and google's TPU datacenter architecture all day.
- zakki 3y agoMind to share the link?
- tgtweak 3y ago[1] https://www.servethehome.com/intel-granite-rapids-xeon-held-at-hot-chips-2023/ https://www.servethehome.com/intel-granite-rapids-xeon-held-... [1b] https://www.servethehome.com/intel-xeon-e-cores-for-next-gen-sierra-forest-and-more-at-hot-chips-2023/ https://www.servethehome.com/intel-xeon-e-cores-for-next-gen... [2]https://www.servethehome.com/google-details-tpuv4-and-its-crazy-optically-reconfigurable-ai-network/ https://www.servethehome.com/google-details-tpuv4-and-its-cr... Very interesting to see the adoption of fiber optic in chips (PIC, photonics in chip/photonic integrated circuit) from so many big players and newcomers.
- daniel-s 3y agohttps://youtube.com/@ServeTheHomeVideo?feature=shared https://youtube.com/@ServeTheHomeVideo?feature=shared The YouTube channel for those who like me are too impatient to ever read.
- NikolaNovak 3y agoLol, that's the story of me and my best friend. I'm far too impatient for YouTube videos. Gimme an article I can scan. He's far too impatient for articles. Give him a YouTube video he can listen to while doing something else. 20 years and we haven't changed each others mind :->
- Patrick-STH 3y agoThanks. We will have more in a bit, and may not get to all of them. I was talking to lots of folks that came to say hi today. Trying to get at least a good portion of these done this week.
- geerlingguy 3y agoThank you for your service. Between your coverage and Dr. Ian Cutress', we can pick up on announcements from events like Hot Chips with a lot more clarity than the PR speak the companies themselves put out.
- matt3210 3y ago8 cores with 528 thread? What’s the math? I assumed 512 but had to reread it
- elromulous 3y agoFrom the article: Here is an interesting one. Intel has a 66-thread-per-core processor with 8 cores in a socket (528 threads?) The cache apparently is not well used due to the workload. This is a RISC ISA not x86.
- wging 3y ago"8-core processor with 66 threads per core." 66*8 = 528. Why 66 is not explained.
- teruakohatu 3y agoMaybe they just couldn't fit 67?
- loeg 3y agoMaybe 2 higher-powered primary threads + 64 aux threads or something. I don't know how that makes sense as part of a single core but I don't have a better guess.
- froogle 3y ago> Here is the actual die photograph and confirmation that this is being done on TSMC 7nm. Yikes, Intel. Has to be a pretty low moment as a chipmaker to have to use your competitor's fabs for something like this.
- epolanski 3y agoIntel has a prototype 1.8nm node which Nvidia already tested and spoken well of. But yes, the 10nm node has been a disaster for Intel and set the company back 5/10 years on the chip making business.
- derefr 3y agoIf not for Intel's 10nm debacle, Apple probably wouldn't have left. All of Apple's early-2010s hardware designs were predicated on Intel's three-years-out promises of thermal+power efficiency for 10nm, that just never materialized.
- hypercube33 3y agoLet's not forget Intel had issues with atom soc chips dying like crazy due to power-on-hours in things like Cisco routers, Nas and other devices around this era too. I think that had a big ripple effect on them to play a cog in their machine around 2018 or so. Yes 10nm+++++ was a big problem, too. Apple was also busy going independent and I think their path is to merge iOS with MacOX someday here so it makes sense to dump x86 in favor of higher control and profit margins.
- Nevermark 3y agoRight. It made no sense for Apple to have complete control over most of their devices, with custom innovations moving between them, and still remain dependent on Intel for one class of devices. Intel downsides for Apple: 1. No reliable control of schedule, specs, CPU, GPU, DPU core counts, high/low power core ratios, energy envelopes. 2. No ability to embed special Apple designed blocks (Secure Enclave, Video processing, whatever, ...) 3. Intel still hasn't moved to on-chip RAM, shared across all core-types. (As far as I know?) 4. The need to negotiate Intel chip supplies, complicated by Intel's plans for other partner's needs. 5. An inability to differentiate Mac's basic computing capabilities from every other PC that continues to use Intel. 6. Intel requiring Apple to support a second instruction architecture, and a more complex stack of software development tools. Apple solved 1000 problems when they ditched Intel.
- rbanffy 3y ago66 threads per core looks more like a barrel processor than anything else. We shouldn’t expect those threads to be very fast, but we can assume that, if the processor has enough work, it should be able to be doing something useful most of the time (rather than waiting for memory).
- twoodfin 3y agoReminds me of Tera, the original SMT. 128 threads per core in 1990! https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=108b3a24274af0aab079bd94ab7c1ee6543563d4 https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&d... (I’d put up money that the DARPA project that funded this work is from the same lineage of TLA interest that got Tera enough money to buy Cray!)
- deleted 3y ago[deleted]
- yvdriess 3y agoTheir multithreaded cores are similar design, yes. It does not do XMT's in-hardware full/empty bit memory access system though.
- pmayrgundter 3y agoFollowing the history here, DARPA also funded work in ~2005 on a project Monarch, that I saw presented at a Google tech talk back then. I believe it refers to the "butterfly" architectures of very scalable interconnects of lightweight processing units Bill Dally was working on the networking side (maybe equiv to the photonics interconnect here) and almost got it up and running at BBN (search for "monarch") http://franki66.free.fr/Principles%20and%20Practices%20of%20Interconnection%20Networks.pdf http://franki66.free.fr/Principles%20and%20Practices%20of%20... Here's some refs for the chip https://slideplayer.com/slide/7739558/ https://slideplayer.com/slide/7739558/ https://viterbischool.usc.edu/news/2007/03/monarch-system-on-a-chip-excels-in-early-testing/ https://viterbischool.usc.edu/news/2007/03/monarch-system-on... 6 main RISC processors with 96 ALUs for the lightweight IO/compute processes
- deleted 3y ago
- ggm 3y agoThey seem to be suggesting if you amortize the die cost and speed consequences of electrical to optical, you can then get pretty much distance-independent speeds (obviously not, but lets limit ourselves to the distance of chip carriers inside a single chassis) interconnect at good rates in optical, with low interference and free routing within the bend radius of the light guides. Maybe I misread it. Maybe the optical component is for something else like die stacking so you get grids of chips on a super carrier, with optical interconnect.
- samstave 3y agoThey had voxels in 1997 when i was there.... the goal was stacking layers and using voxels in the vertical stack
- Already__Taken 3y agogetting the cores apart would do a lot for sinking the heat
- seeknotfind 3y agoTime to finish rewriting all code to be event driven, io_uring, etc.
- convolvatron 3y agoin this kind of architecture, its generally more fruitful to leave the asynchrony to the hardware. the tera mta, which other people have mentioned has/had hardware synchronization in the memory system to effect this. there were no interrupts, just a thread waiting for someone to wake it up.
- gautamcgoel 3y agoDid I read the article correctly? Is there 32GB of DRAM on-chip? Or was the DRAM just standard DIMMs?
- wmf 3y agoIt's regular DDR5.
- geerlingguy 3y ago[edit: I think I'm wrong!] I'm pretty sure this is HBM (High Bandwidth Memory) on the same substrate: https://en.wikipedia.org/wiki/High_Bandwidth_Memory https://en.wikipedia.org/wiki/High_Bandwidth_Memory There are some other explainers out there that go into more detail, but Nvidia is also doing this with Grace Hopper (I think?), and Apple with their M-series chips. Update: It looks like it's just DDR5 ("custom DDR5-4400 DRAM") in this case.
- felixg3 3y agoApple is not using HBM on M-Series chips, although I bet the speed benefit would be massive.
- yvdriess 3y agoNot on-chip no, it's still DDR5 DIMMs. What is cool about is that it is using custom DIMMs and memory controllers to do 8B-granularity accesses. Plus, each core has its own MC, as you can see on the die shot. If each MC manages 4GB of DRAM, that would explain the 32GB per chip.
- gautamcgoel 3y agoCan you elaborate on the granularity? Why is that important?
- yvdriess 3y agoYour regular DRAM memory controller will use the 64B bus to pull in a single 64B line of memory. In your modern x86 systems, that's equal to a cache line. If you are only accessing a single 4B or 8B element of that cache line >80% of the time, as shown on the slides, you are wasting 7/8th of all memory bandwidth with irrelevant data. If you were to use that 64B memory bus to access 8x different 8B memory locations, you get a large boost to your effective bandwidth.
- shae 3y agoThis would be perfect for graph reduction and dataflow programming. I could build some really col things with these if they ever go into production.
- shrubble 3y agoSun did something similar many years ago, but they abandoned it in later UltraSPARC CPUs. Was it that the threads were starved? Did they find that less cores but faster was better? I can't find out much detail about it. Perhaps HN user bcantrill will give us the inside scoop :-)
- tyingq 3y agoI used them in the heyday. There were workloads where they were fantastic, but anything that needed good single-core performance suffered. It also often required much more tuning of parameters to perform, or recompilation, etc. For me, it also coincided with lots more need to use SSL, which had been optimized well for x86 but not Sparc. So now you were dealing with more complexity via SSL offload cards, or reverse proxies. Basically, just too fussy to make them work well outside a few niche areas. Maybe not a big factor, but it also was bothersome for sysadmins because much of the work we had to do was serial, single core, etc. Meaning it showed it's worst side to the group that usually signed the vendor checks.
- brucethemoose2 3y agoMarvell made an SMT8 ARM CPU with "768 Threads Per Node" https://www.servethehome.com/marvell-thunderx3-arm-server-cpu-with-768-threads-in-2020/ https://www.servethehome.com/marvell-thunderx3-arm-server-cp... IIRC it was targeted at database workloads, and the pitch was the same: if the core is usually twiddling its thumbs waiting on RAM, it might as well work on another thread in the meantime. And I guess IBM and Zen4C kinda fufill this demand, but more SMT16 cloud instances explicity targeted at these low IPC loads would be neat.
- pyinstallwoes 3y agoI never read or heard someone say “mind as well..” is that common where you’re from? I’ve only ever heard “might as well…” Interesting thank you!
- carbotaniuman 3y agoFeels like a typo I think, it doesn't seem to be a thing from a Google search.
- pyinstallwoes 3y agoIt reminds me of the difference I saw in Europe when signs posted may say “mind your step” instead of “watch your step”
- galaxyLogic 3y agoRight, the London subway (used to) have an announcement on every stop: "Mind the Gap". It is weird and wonderful.
- brucethemoose2 3y agoYep, typo. It is late...
- paulmd 3y agoNiagara (Ultrasparc T1/T2) did the same thing. CMT8/SMT8 seems to be a sweet spot for these kinds of barrel processor-esque designs.
- ConanRus 3y ago[dead]
- londons_explore 3y agoIt really seems like Intel is designing this chip to support a very specific workload, when it would have been a better use of everyone's time and money to just rewrite the workload to work well on normal chips...
- wmf 3y agoThat graph workload fundamentally cannot work well on normal chips.
- londons_explore 3y agoCitation needed. Huge sparse graphs can be processed fairly efficiently on both CPU's and GPU's, but the code has to be written with the architecture in mind.
- yvdriess 3y agoTheir inefficiency at large-scale graph problems is the entire reason DARPA wrote out the program that funded this chip.
- danbruc 3y agoI have no expertise in this area, but I think the presentation explains the issue quite well. The workloads they consider have a large number of indirection and poor memory locality, so a lot of memory operations have to wait for cache misses, but you have to do the same thing a lot of times independently with different data. Normal multithreading is not a solution because it is not granular enough, you can not context switch in the middle of each memory access to run a different thread while waiting for the memory access to complete. You could manually unroll loops and instead of only following one path through the graph you could follow several paths at the same time by interleaving their operations. While this will be able to hide the waiting times because you can continue working on other paths, it will make your code more complex and increase register pressure as you still have the same number of registers but are operating on multiple independent paths. Letting the hardware interleave many parallel paths will keep your code simpler and as each thread has its own registers also not increase register pressure.
- mrweasel 3y agoI can't help picturing the OpenBSD developers getting their hands on this and promptly disabling 65 threads per core due to security concerns.
- belter 3y agoThose who sacrifice security to performance, deserve neither :-)
- coldtea 3y agoFounding fathers aside, if you're not connected to the internet or even wider LAN, but on some private lab running specific workloads, you don't need security from malicious side-loaded apps.
- belter 3y agoOh yes you do. "14 Popular Air-Gapped Data Exfiltration Techniques Used to Steal the Data" - https://thesecmaster.com/14-popular-air-gapped-data-exfiltration-techniques-used-to-steal-the-data/ https://thesecmaster.com/14-popular-air-gapped-data-exfiltra... "A Survey on Air-Gap Attacks: Fundamentals, Transport Means, Attack Scenarios and Challenges" - https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10054827/ https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10054827/
- coldtea 3y agoThe data could be public anyway, like publicly funded research data. Not every number crunching means secrecy. Also none of the above are about software level security. You'll probably not doing those anyway, even if you have all the security fixes for cpu timing stuff (as was the context) enabled.
- aitchnyu 3y agoCan I have context on whether they are innovation killers or prophets vindicated after years of mockery or somewhere in between?
- tiffanyh 3y agoUse case? What would be a good use case for a high-thread / low-core chip? Parallelism, like Erlang systems?
- worthless-trash 3y agoI benchmarked knights-phi at the time (the add on card) for erlang, it was very impressive. Sadly it never took off.
- yvdriess 3y agoGraph workloads and other types of sparse compute. https://www.darpa.mil/program/hierarchical-identify-verify-exploit https://www.darpa.mil/program/hierarchical-identify-verify-e...
- dschuetz 3y agoThis seems more like a proof-of-concept CPU rather than a marketable product, highly specialized, problems and workloads that it solves yet to be found. I anticipate that photonics will be introduced to general-purpose computing in the years to come, even if only to get a handle on the rising excess heat problems. Most notable is the 10 -> 7 nm process.
- lcnmrn 3y agoIt will be great to have a setting in the OS to set number of threads per core.
- mirekrusin 3y agoCan you do efficient matrix multiplication on photonics? Can it be further exploited by not requiring it to be 100% precise, ie. when close approximation is good enough?
- Symmetry 3y agoIn this case photonics is used to transport data from one place to another. An electrical bit is converted to a photonic bit, moves across the chip, and then is converted back to an electrical bit. I'm not aware of any even vaguely practical photonic logic gates that would start to allow us to do computation in light.
- DesiLurker 3y agoyes, see https://lightmatter.co https://lightmatter.co
- specialist 3y agoNoob question: Can/will silicon photonics help with the clock?
- hinkley 3y agoSo what's the instructions per clock on a barrel processor?