14 ms·

Moore’s Law is dead – Long live the chiplet

157 points by chclau 4y ago

314 4y ago
The rising cost of software in the design process is startling. I wonder what opportunity there is for new entrants to reduce that cost.
- MHAlliance 4y ago
  Jeff Dean's recent talk on ML for hardware design seems like a great application of the tech in a space where we are seeing design process costs balloon (see https://www.youtube.com/watch?v=FraDFZ2t__A https://www.youtube.com/watch?v=FraDFZ2t__A).
- atty 4y ago
  I was actually wondering if someone could explain where that cost increase is coming from. I know the design rules get more complicated as the process node shrinks, but I thought most of those design rules are essentially “taken care of”, because customers use building blocks from the foundry that already have those design rules baked in? And it’s still using the same software I thought?
  - deleted 4y ago
    [deleted]
  - adgjlsfhk1 4y ago
    a lot of it is that to get continued gains, you run out of easy stuff to optimize. when Moore was alive and well, the job of chip designers was to build abstractions that let them cheaply scale down their designs without introducing too much overhead. now, is you want to announce 30% gen on gen improvement, you can only count on the fab to give you half of that (and even that has gotten harder. co-optimization is now needed, but is really hard). for the other half, you now need to hunt down every last inefficiency that you previously accepted to make your life easier. pure digital signals go to pam4. layout becomes less regular. you start trying to optimize the whole chip rather than just combining optimized pieces. then in 3 years, you have to find another 15% and the process repeats, but this time you have used up all the low hanging improvements.
froggertoaster 4y ago
Moore's Law is dead - can anyone think of a more cliche article title in the tech world?
- wjnc 4y ago
  “20xx - Year of the Linux desktop”
  - cm2187 4y ago
    2xxx
    - u801e 4y ago
      Hopefully sometime before 2038.
    - Ygg2 4y ago
      That's too optimistic :P
    - zimpenfish 4y ago
      /1999|2\d{3}/ - "Dirk Hohndel, who was then the chief Linux and open-source technologist at Intel, predicted that in 1999, Linux would penetrate the PC desktop market and displace Windows."[1] [1] https://www.howtogeek.com/676963/why-desktop-linux-still-matters/ https://www.howtogeek.com/676963/why-desktop-linux-still-mat...
      - xattt 4y ago
        People in 1999 could not imagine Android devices.
  - froggertoaster 4y ago
    That's a good one!
- dragonelite 4y ago
  Moore's Law is transisters per square mm or something like that. Just drop a second layer on top with 3d fabbing and im sure moore's law will go on for a decade. inbe4 we have 2,4,8,16,32 etc layer architectures in the future.
reillyse 4y ago
Moore’s law was a marketing road map for intel. It was basically a monopolistic warning from one of the founders not to release new products too fast so the company wouldn’t burn out. It worked. But it’s not some scientific or physical law and I hate when people refer to it as such.
- ac29 4y ago
  > Moore’s law was a marketing road map for intel. According to the article, Moore's Law predates the founding of Intel by several years.
- ddalex 4y ago
  Did Moore law apply to other chip manufacturers too? Intel can't dictate the technology advances of other competitors
  - urthor 4y ago
    Moore's law applied to transistor density, period. So memory and logic equally.
- Shorel 4y ago
  Even more: It was about the price per transistor. Not about transistor size of performance. So it was an economic insight, more than anything else.
atulvi 4y ago
If I got a penny everytime I hear about the death of Moore's law..
- Karellen 4y ago
  If I got one penny the first time I heard about the death or Moore's law, two pennies the second time, four pennies the next...
karmasimida 4y ago
Latest death of Moore Law Shocking
transpute 4y ago
DARPA ERI (Electronics Resurgence Initiative) has promoted chiplet interoperability and included $100M funding for open-source EDA tools, https://www.eetimes.com/darpa-unveils-100m-eda-project/ https://www.eetimes.com/darpa-unveils-100m-eda-project/ > With $100 million in funding, the IDEAS and POSH programs ... aim to combat the growing complexity and cost of designing chips, now approaching $500 million for a bleeding-edge SoC. Essentially, POSH aims to create an open-source library of silicon blocks, and IDEAS hopes to spawn a variety of open-source and commercial tools to automate testing of those blocks and knitting them into SoCs and printed circuit boards. If successful, the programs “will change the economics of the industry,” enabling companies to design in relatively low-volume chips that would be prohibitive today. 2017 vision, slide #22, https://www.darpa.mil/attachments/eri_design_proposers_day.pdf https://www.darpa.mil/attachments/eri_design_proposers_day.p... My DARPA dream $ git clone https://github.com/darpa/idea $ git clone https://github.com/darpa/posh $ cd posh $ make soc42 ERI Summit 2019, Intelligent Design of Electronic Assets (IDEA) & Posh Open Source Hardware (POSH), https://youtube.com/watch?v=pJubnAN3VKw https://youtube.com/watch?v=pJubnAN3VKw UCSD OpenRoad, https://theopenroadproject.org/ https://theopenroadproject.org/ & https://vlsicad.ucsd.edu/Publications/Conferences/378/c378.pdf https://vlsicad.ucsd.edu/Publications/Conferences/378/c378.p... > OpenROAD is a front-runner in open-source semiconductor design automation tools and know-how. Our project reduces barriers of access and tool costs to democratize system and product innovation in silicon. The OpenROAD tool and flow provide autonomous, no-human-in-the-loop, 24-hour RTL-GDSII capability to support low-overhead design exploration and implementation through tapeout. We welcome a diverse community of designers, researchers, enthusiasts and entrepreneurs who use and contribute to OpenROAD to make a far-reaching impact. https://semiengineering.com/will-open-source-eda-work/ https://semiengineering.com/will-open-source-eda-work/ > All the big EDA providers, as well as leading chip companies, are active contributors to ERI projects. In fact, Cadence, Synopsys, Mentor, NXP, Intel, IBM, Intel, Qualcomm, Arm, Nvidia, Analog Photonics, SRI International and Applied Materials all have contributed speakers and engineers or materials to ERI effort ... the key to getting industry players to accept open-source EDA is whether it makes the design process more efficient without breaking anything—and whether it is possible to extract decades worth of design experience from libraries of millions of existing designs and use that to spot errors in real time in existing designs.
tester756 4y ago
Jim Keller: Moore’s Law is Not Dead https://www.youtube.com/watch?v=oIG9ztQw2Gc https://www.youtube.com/watch?v=oIG9ztQw2Gc
brundolf 4y ago
Lotta people here not reading the article: > However, as it has in the past, the semiconductor ecosystem is adapting and as Chiplet technology builds traction, we will very likely see a period of accelerating innovation and new market opportunities opening as we move forward. The whole premise is that chip innovation (and overall computing power) is continuing to accelerate, even though "Moore's Law as we've known it" has ended
- ordu 4y ago
  I'd say that the premise of the article is captured in the title perfectly. One needn't to read the article to get it. So, we can strengthen your assertion and to say that "lotta people here are not reading the title." People react to the first part of the title. Seems they are really exasperated by all these repeated deaths of Moore's law.
  - Eisenstein 4y ago
    Does Moore's law require transistors to double on a chip made from a single die?
  - brundolf 4y ago
    In the title it's a little subtle due to the wordplay and terminology, but yeah, it is present. Definitely a lot of knee-jerking going on
aargh_aargh 4y ago
For dummies like me who didn't know what a chiplet is: https://en.wikipedia.org/wiki/Chiplet https://en.wikipedia.org/wiki/Chiplet This seems to be about the third reason listed: > Known good die (KGD): chiplets can be tested before assembly, improving the yield of the final device Problem: > In general, a killer defect is defined as a defect that is 20% the size of the fabrication node. For > example, a defect that is less than 9nm may be acceptable for the 45nm fabrication node, but a defect > larger than 2.8nm would be defined as a “killer” defect for the 14nm fabrication node. For the 5nm > fabrication node, a defect measuring only 1nm could be a killer. > > This is one of the primary reasons that it has become increasingly difficult to yield large monolithic > ICs (as measured in die area) when using leading edge fabrication process technology Solution: I understood it from the visual explanation in the first chip image (AMDArt2 png) and its description in this article: https://www.nextplatform.com/2021/06/09/amd-on-why-chiplets-and-why-now/ https://www.nextplatform.com/2021/06/09/amd-on-why-chiplets-...
- tyingq 4y ago
  AMD's EPYC-Rome processor, helpful to look at after looking at your link, as the chiplets are nice and visible: https://cdn.wccftech.com/wp-content/uploads/2018/11/AMD-EPYC-Rome-64-Core-CPU.png https://cdn.wccftech.com/wp-content/uploads/2018/11/AMD-EPYC...
- londons_explore 4y ago
  Is silicon manufacturing done entirely in a vacuum yet? Because a vacuum pretty eliminates dust - with no air, dust just falls towards either the ground (if it is uncharged), or towards a positive or negatively charged surface (if the dust particle itself is charged).
  - rcxdude 4y ago
    No (at least not entirely: some steps are done in a vacuum or very low pressure), in part because it's harder to get a vacuum than clean enough air. Also it would cause a lot of other problems as well as not solving the whole problem: a lot of processing steps involve applying chemicals to the surface of the wafer, washing off those chemicals, or otherwise handling liquids which would boil in a vacuum. Those chemicals (including just plain water), also carry the same risk of introducing 'killer particles', so they are also a big part of the process control needed in a fab (the levels of contaminants in water that is required on modern process nodes is actually lower than can be detected practically with current technology: the last levels of water purification are effectively done blind, with yield as the only feedback mechanism).
theaeolist 4y ago
Even if the Moore's law is not dead, single-thread performance and clock frequency have plateaued 10 years ago. This is the key factor. Because of heating even if you squeeze more transistors onto a chip you need to reduce the clock, so even if you may get higher computational throughput the latency will go down. And this is another argument for chiplets or any other alternative computational architectures.
- Uehreka 4y ago
  Have clock speeds really plateaued? Sure it’s not “double every 18 months”, but in mid 2018 I bought an Intel 8700K that turbo’d to 4.7GHz and could (with liquid metal, dark magic and luck) overclock to exactly 5GHz. I remember people saying progress was slowing down, that we might not make it to 6GHz. 4.5 years later and Intel is bragging that their upcoming topline CPU will run 6GHz stock. I suppose one could call this a plateau compared to the good old days of the 80s and 90s, but it’s definitely still progress.
  - dontlaugh 4y ago
    Part of why that happens is Intel selling chips closer to the red line. You need cooling similar to what used to be exclusive to overclocking just to keep the stock CPU cool.
    - MrFoof 4y ago
      Yep. We're apparently finding out that it's mostly a waste of electricity to get an extra 5% performance due to how far outside the efficiency sweet spot chips are being pushed. Not just Intel either. AMD has joined the game as of Zen 4, and NVIDIA's been playing it with their GPUs forever as well. Zen 4 desktop CPUs appear to have (as expected) virtually unchanged single core performance, and maybe 5% reduced multi-core performance, on CPU-bound workloads by reducing the power limit to cut total power consumption -- by over a 100W reduction in the case of the new 7950X! Granted, Intel's been doing that forever -- reign in Alder Lake and its power consumption also comes way down, again for barely a performance hit in CPU-bound multi-core tasks. ----- Enthusiast grade CPUs and GPUs are basically sold in the equivalent of a TV's retail "demo mode" now -- where a TV has max brightness, contrast and saturation that you'd NEVER use, but is intended to just grab a customer's attention as they walk by. Being pushed so far outside of their efficiency sweet spot just to get that extra 5% to "win benchmarks", when outside of specific use cases (and even if you actually need that 5%!) you're just consuming 50-100% more electricity for utterly marginal gains. What a waste of resources! All so children (or people who still act like them) can feel better about a purchase as they argue on the internet over nothing worth arguing about.
lukaesch 4y ago
Wouldn’t this mean that we should focus on writing more efficient code than before? Especially in the startup space I saw companies building software with the hypothesis “users need the latest device for our product and they will get faster anyway so we don’t need optimize our code. Instead we deliver features on max speed skipping optimizations and wait until our users upgraded to newer devices during the coming 2-4 years”.
- mildmotive 4y ago
  It’s offloading the cost to the customer. It is way cheaper to develop in some famous interpreted language than creating a set of robust compiled binaries. As long as customers can pay up for newer hardware we will keep seeing clunky UIs that can barely handle 20 list items of variable size without noticeable lag on a modern computer. I don’t even blame the companies for doing this. The benefit to cost ratio of using idk C++ for everything is just too bad.
  - Ma8ee 4y ago
    But the inefficiencies you sometimes see today can’t even be explained with any bad choice of language. You can create more than fast enough programs with interpreted languages with garbage collection. But then of course you need to know at least a little bit about data structures and not doing dozens of REST calls anytime anyone taps the screen.
    - lpedrosa 4y ago
      What if doing dozens of REST calls is effectively the product?
      - Ma8ee 4y ago
        Could you explain? I’ve got a hard time imagining a user interested in the rest calls themselves.
    - mildmotive 4y ago
tapanjk 4y ago
> Obviously, given these data, volume is VERY important in business models that operate with high fixed and low variable costs. Off-topic but I wonder how much cheaper mobile phones would be if the manufacturers did not have to come up with a hardware design update every year or so? What if mobile phones were built to last longer, which would reduce the cost per phone due to high volume? Of course, I am not suggesting this is good for business but as a mere thought experiment.
- alexvoda 4y ago
  At this point the most direct and highest impact way of making phones last longer is forcing Qualcomm to support their chipsets for more than 2 years.
somat 4y ago
I am not convinced moore's law no longer holds true, consider that there is a third dimension that no one has yet figured out. I am no silicon engineer but I suspect a chip that fully takes advantage of the third dimension would be something like a sponge full of built in channels for the working fluid to remove heat. First however I suspect you will see chiplets arranged vertically like heatsink fins and the whole cpu would effectively be the water block, basically a vlsi version of the cray 3
- deleted 4y ago
  [deleted]
- urthor 4y ago
  https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/3DFabric.htm https://3dfabric.tsmc.com/english/dedicatedFoundry/technolog... What you're describing is called 3D stacking, and it works. It's just extraordinarily complex to resolve the intra-die latency issues, and many others, when going vertical. Hence expensive.
  - petra 4y ago
    3D is already being used for ram/flash IC's. That's possible because most memory cells aren't being used in a memory chip - so heat density is reasonable. 3D is also used in AMD's 3D cache. But 3D logic on logic is more complicated because of heat issues. AFAIK there's no workable technical solution for that yet.
- threatripper 4y ago
  Heat removal is basically a 2D problem. A 3D pipe has a 2D cross section in which fluid can transport heat. Right now we are mostly limited by heat removal, so adding more height to the chip doesn't help anything with the heat. Also, the chips are already many layers thick and each layer means processing steps which means time and money. If you look into flash memory which aren't limited by heat, they have dozens of functional layers already and then we also stack those silicon wafers.
sitkack 4y ago
Cerebras' WFE is just a large chiplet.
BirAdam 4y ago
Unless I’m missing something, the article did mention Moore’s law proper with transistor density doubling every 18 months, but then meandered to talk about other things. M1 has 16 billion transistors thanks to TSMC. Each new node has delivered on Moore’s law with AMD and Apple. I don’t doubt that Moore’s law will stop. I can even say that it Moore’s law may have failed from time to time, but the spirit of the law lives. Moving to chiplets doesn’t change transistor density. This is a packaging feature and not a fabrication feature. This is done for manufacturing cost reduction and yield improvements.
- wongarsu 4y ago
  One interesting point is that even if Moore's law stops or slows down, chiplets allow us to increase transistor count independently of transistor density. Thus keeping alive the spirit of the law (processors get more and more transistors).
  - bjourne 4y ago
    Maybe. How many times can you double the size of a 25mm^2 chip before it becomes impractically large?
    - WithinReason 4y ago
      Until you turn it into a 25mm^3 chip
- urthor 4y ago
  Moore's law is: Transistor density doubling every 18 months for a similar cost. https://t7m8e9c8.rocketcdn.me/wp-content/uploads/2020/09/precio-oblea-tsmc-5nm.jpg https://t7m8e9c8.rocketcdn.me/wp-content/uploads/2020/09/pre... https://en.wikipedia.org/wiki/Moore%27s_law#cite_note-Moore_1965-1 https://en.wikipedia.org/wiki/Moore%27s_law#cite_note-Moore_... By those terms, Moore's law is totally extinct. Folk haven't noticed however, because the "leading edge" logic manufacturers have 60% gross margins. The vast majority of their costs are in design, distribution and overhead. Price rises of 30% to 100% have disguised that the cost of manufacturing the silicon is an order of magnitude more than a decade ago. Granted, the above numbers are not the actual inflation adjusted wafer cost for leading edge nodes. But, $16,000 for a 300mm wafer is extraordinary.
PaulHoule 4y ago
Moore’s law is alive but the benefits are diminishing. Until 2005 or so, shrinking transistors automatically increased speed and reduced power consumption. When that ran out of steam, the industry went to multi core and massive parallelism with GPUs. Until recently each shrink also lowered the cost per transistor, but that seems to have run out also and has something to do with why Intel was stuck at 14nm for so long and why new GPU prices are so insane despite a collapse in demand and resolution of the supply chain crisis for high end chips. Chiplets at best are neutral with regard to cost. If manufacturing overhead is low, two chiplets give you twice the transistors at twice the cost. The industry did not pursue chiplets with a lot of vigor until now because it was a less competitive approach to scaling than shrinking transistors until now.
- bjourne 4y ago
  The reason Intel was "stuck" at 14 nm was because it took Extreme ultraviolet lithography (EUV) many years longer to become viable than was predicted. Prices may have more to do with the EUV market being dominated by ASML which has serious trouble producing lithography machines fast enough to meet demand.
  - PaulHoule 4y ago
    If it’s not one thing it’s another. If progress continues then they will need some other expensive machine. Either that or they’ll try to stretch the life of EUV the same way Intel tried to delay EUV with extreme multiple patterning. It seems to me though that the ASML machines ought to get some competition from something more like a free electron laser.
  - adrian_b 4y ago
    No, Intel was "stuck" at 14 nm because they believed that they will succeed to scale down the transistor sizes a lot more, without using EUV, as Pat Gelsinger has just explained in a long interview in the Verge. However they failed to implement with good results the methods that they had hoped to work, while the others, i.e. TSMC and Samsung had much more realistic roadmaps, which added EUV at the right moment. Intel was not stalled by waiting for EUV, on the contrary they were not prepared for the transition that was necessary when EUV was eventually ready. https://www.theverge.com/2022/10/4/23385652/pat-gelsinger-intel-chips-act-ohio-manufacturing-chip-shortage https://www.theverge.com/2022/10/4/23385652/pat-gelsinger-in...
Qem 4y ago
At least Proebsting's Law doesn't look so depressing anymore, by comparison: https://proebsting.cs.arizona.edu/law.html https://proebsting.cs.arizona.edu/law.html
WithinReason 4y ago
The number of people predicting the end of Moore's Law doubles every 2 years
ilaksh 4y ago
The history of computing is moving from one paradigm to another. We are well past the fast speedups in single thread transistor-based performance phase and into the hyper-parallelization phase. 3d stacking is another innovation that can help. But I think within a decade or two there will be a move away from silicon-only transistors to something like memristors or some type of optical or optoelectronic system that hasn't even been invented yet. This will provide some iterations with again radical parallel interconnect and quite possibly single thread speedups.
chatterhead 4y ago
deleted 4y ago
[deleted]

157 points by chclau 4y ago

314 4y ago

The rising cost of software in the design process is startling. I wonder what opportunity there is for new entrants to reduce that cost.

MHAlliance 4y ago
Jeff Dean's recent talk on ML for hardware design seems like a great application of the tech in a space where we are seeing design process costs balloon (see https://www.youtube.com/watch?v=FraDFZ2t__A https://www.youtube.com/watch?v=FraDFZ2t__A).
atty 4y ago
I was actually wondering if someone could explain where that cost increase is coming from. I know the design rules get more complicated as the process node shrinks, but I thought most of those design rules are essentially “taken care of”, because customers use building blocks from the foundry that already have those design rules baked in? And it’s still using the same software I thought?
- deleted 4y ago
  [deleted]
- adgjlsfhk1 4y ago
  a lot of it is that to get continued gains, you run out of easy stuff to optimize. when Moore was alive and well, the job of chip designers was to build abstractions that let them cheaply scale down their designs without introducing too much overhead. now, is you want to announce 30% gen on gen improvement, you can only count on the fab to give you half of that (and even that has gotten harder. co-optimization is now needed, but is really hard). for the other half, you now need to hunt down every last inefficiency that you previously accepted to make your life easier. pure digital signals go to pam4. layout becomes less regular. you start trying to optimize the whole chip rather than just combining optimized pieces. then in 3 years, you have to find another 15% and the process repeats, but this time you have used up all the low hanging improvements.

froggertoaster 4y ago

Moore's Law is dead - can anyone think of a more cliche article title in the tech world?

wjnc 4y ago
“20xx - Year of the Linux desktop”
- cm2187 4y ago
  2xxx
  - u801e 4y ago
    Hopefully sometime before 2038.
  - Ygg2 4y ago
    That's too optimistic :P
  - zimpenfish 4y ago
    /1999|2\d{3}/ - "Dirk Hohndel, who was then the chief Linux and open-source technologist at Intel, predicted that in 1999, Linux would penetrate the PC desktop market and displace Windows."[1] [1] https://www.howtogeek.com/676963/why-desktop-linux-still-matters/ https://www.howtogeek.com/676963/why-desktop-linux-still-mat...
    - xattt 4y ago
      People in 1999 could not imagine Android devices.
- froggertoaster 4y ago
  That's a good one!
dragonelite 4y ago
Moore's Law is transisters per square mm or something like that. Just drop a second layer on top with 3d fabbing and im sure moore's law will go on for a decade. inbe4 we have 2,4,8,16,32 etc layer architectures in the future.

reillyse 4y ago

Moore’s law was a marketing road map for intel. It was basically a monopolistic warning from one of the founders not to release new products too fast so the company wouldn’t burn out. It worked. But it’s not some scientific or physical law and I hate when people refer to it as such.

ac29 4y ago
> Moore’s law was a marketing road map for intel. According to the article, Moore's Law predates the founding of Intel by several years.
ddalex 4y ago
Did Moore law apply to other chip manufacturers too? Intel can't dictate the technology advances of other competitors
- urthor 4y ago
  Moore's law applied to transistor density, period. So memory and logic equally.
Shorel 4y ago
Even more: It was about the price per transistor. Not about transistor size of performance. So it was an economic insight, more than anything else.

atulvi 4y ago

If I got a penny everytime I hear about the death of Moore's law..

Karellen 4y ago
If I got one penny the first time I heard about the death or Moore's law, two pennies the second time, four pennies the next...

karmasimida 4y ago

Latest death of Moore Law Shocking

transpute 4y ago

DARPA ERI (Electronics Resurgence Initiative) has promoted chiplet interoperability and included $100M funding for open-source EDA tools, https://www.eetimes.com/darpa-unveils-100m-eda-project/ https://www.eetimes.com/darpa-unveils-100m-eda-project/ > With $100 million in funding, the IDEAS and POSH programs ... aim to combat the growing complexity and cost of designing chips, now approaching $500 million for a bleeding-edge SoC. Essentially, POSH aims to create an open-source library of silicon blocks, and IDEAS hopes to spawn a variety of open-source and commercial tools to automate testing of those blocks and knitting them into SoCs and printed circuit boards. If successful, the programs “will change the economics of the industry,” enabling companies to design in relatively low-volume chips that would be prohibitive today. 2017 vision, slide #22, https://www.darpa.mil/attachments/eri_design_proposers_day.pdf https://www.darpa.mil/attachments/eri_design_proposers_day.p... My DARPA dream $ git clone https://github.com/darpa/idea $ git clone https://github.com/darpa/posh $ cd posh $ make soc42 ERI Summit 2019, Intelligent Design of Electronic Assets (IDEA) & Posh Open Source Hardware (POSH), https://youtube.com/watch?v=pJubnAN3VKw https://youtube.com/watch?v=pJubnAN3VKw UCSD OpenRoad, https://theopenroadproject.org/ https://theopenroadproject.org/ & https://vlsicad.ucsd.edu/Publications/Conferences/378/c378.pdf https://vlsicad.ucsd.edu/Publications/Conferences/378/c378.p... > OpenROAD is a front-runner in open-source semiconductor design automation tools and know-how. Our project reduces barriers of access and tool costs to democratize system and product innovation in silicon. The OpenROAD tool and flow provide autonomous, no-human-in-the-loop, 24-hour RTL-GDSII capability to support low-overhead design exploration and implementation through tapeout. We welcome a diverse community of designers, researchers, enthusiasts and entrepreneurs who use and contribute to OpenROAD to make a far-reaching impact. https://semiengineering.com/will-open-source-eda-work/ https://semiengineering.com/will-open-source-eda-work/ > All the big EDA providers, as well as leading chip companies, are active contributors to ERI projects. In fact, Cadence, Synopsys, Mentor, NXP, Intel, IBM, Intel, Qualcomm, Arm, Nvidia, Analog Photonics, SRI International and Applied Materials all have contributed speakers and engineers or materials to ERI effort ... the key to getting industry players to accept open-source EDA is whether it makes the design process more efficient without breaking anything—and whether it is possible to extract decades worth of design experience from libraries of millions of existing designs and use that to spot errors in real time in existing designs.

tester756 4y ago

Jim Keller: Moore’s Law is Not Dead https://www.youtube.com/watch?v=oIG9ztQw2Gc https://www.youtube.com/watch?v=oIG9ztQw2Gc

brundolf 4y ago

Lotta people here not reading the article: > However, as it has in the past, the semiconductor ecosystem is adapting and as Chiplet technology builds traction, we will very likely see a period of accelerating innovation and new market opportunities opening as we move forward. The whole premise is that chip innovation (and overall computing power) is continuing to accelerate, even though "Moore's Law as we've known it" has ended

ordu 4y ago
I'd say that the premise of the article is captured in the title perfectly. One needn't to read the article to get it. So, we can strengthen your assertion and to say that "lotta people here are not reading the title." People react to the first part of the title. Seems they are really exasperated by all these repeated deaths of Moore's law.
- Eisenstein 4y ago
  Does Moore's law require transistors to double on a chip made from a single die?
- brundolf 4y ago
  In the title it's a little subtle due to the wordplay and terminology, but yeah, it is present. Definitely a lot of knee-jerking going on

aargh_aargh 4y ago

For dummies like me who didn't know what a chiplet is: https://en.wikipedia.org/wiki/Chiplet https://en.wikipedia.org/wiki/Chiplet This seems to be about the third reason listed: > Known good die (KGD): chiplets can be tested before assembly, improving the yield of the final device Problem: > In general, a killer defect is defined as a defect that is 20% the size of the fabrication node. For > example, a defect that is less than 9nm may be acceptable for the 45nm fabrication node, but a defect > larger than 2.8nm would be defined as a “killer” defect for the 14nm fabrication node. For the 5nm > fabrication node, a defect measuring only 1nm could be a killer. > > This is one of the primary reasons that it has become increasingly difficult to yield large monolithic > ICs (as measured in die area) when using leading edge fabrication process technology Solution: I understood it from the visual explanation in the first chip image (AMDArt2 png) and its description in this article: https://www.nextplatform.com/2021/06/09/amd-on-why-chiplets-and-why-now/ https://www.nextplatform.com/2021/06/09/amd-on-why-chiplets-...

tyingq 4y ago
AMD's EPYC-Rome processor, helpful to look at after looking at your link, as the chiplets are nice and visible: https://cdn.wccftech.com/wp-content/uploads/2018/11/AMD-EPYC-Rome-64-Core-CPU.png https://cdn.wccftech.com/wp-content/uploads/2018/11/AMD-EPYC...
londons_explore 4y ago
Is silicon manufacturing done entirely in a vacuum yet? Because a vacuum pretty eliminates dust - with no air, dust just falls towards either the ground (if it is uncharged), or towards a positive or negatively charged surface (if the dust particle itself is charged).
- rcxdude 4y ago
  No (at least not entirely: some steps are done in a vacuum or very low pressure), in part because it's harder to get a vacuum than clean enough air. Also it would cause a lot of other problems as well as not solving the whole problem: a lot of processing steps involve applying chemicals to the surface of the wafer, washing off those chemicals, or otherwise handling liquids which would boil in a vacuum. Those chemicals (including just plain water), also carry the same risk of introducing 'killer particles', so they are also a big part of the process control needed in a fab (the levels of contaminants in water that is required on modern process nodes is actually lower than can be detected practically with current technology: the last levels of water purification are effectively done blind, with yield as the only feedback mechanism).

theaeolist 4y ago

Even if the Moore's law is not dead, single-thread performance and clock frequency have plateaued 10 years ago. This is the key factor. Because of heating even if you squeeze more transistors onto a chip you need to reduce the clock, so even if you may get higher computational throughput the latency will go down. And this is another argument for chiplets or any other alternative computational architectures.

Uehreka 4y ago
Have clock speeds really plateaued? Sure it’s not “double every 18 months”, but in mid 2018 I bought an Intel 8700K that turbo’d to 4.7GHz and could (with liquid metal, dark magic and luck) overclock to exactly 5GHz. I remember people saying progress was slowing down, that we might not make it to 6GHz. 4.5 years later and Intel is bragging that their upcoming topline CPU will run 6GHz stock. I suppose one could call this a plateau compared to the good old days of the 80s and 90s, but it’s definitely still progress.
- dontlaugh 4y ago
  Part of why that happens is Intel selling chips closer to the red line. You need cooling similar to what used to be exclusive to overclocking just to keep the stock CPU cool.
  - MrFoof 4y ago
    Yep. We're apparently finding out that it's mostly a waste of electricity to get an extra 5% performance due to how far outside the efficiency sweet spot chips are being pushed. Not just Intel either. AMD has joined the game as of Zen 4, and NVIDIA's been playing it with their GPUs forever as well. Zen 4 desktop CPUs appear to have (as expected) virtually unchanged single core performance, and maybe 5% reduced multi-core performance, on CPU-bound workloads by reducing the power limit to cut total power consumption -- by over a 100W reduction in the case of the new 7950X! Granted, Intel's been doing that forever -- reign in Alder Lake and its power consumption also comes way down, again for barely a performance hit in CPU-bound multi-core tasks. ----- Enthusiast grade CPUs and GPUs are basically sold in the equivalent of a TV's retail "demo mode" now -- where a TV has max brightness, contrast and saturation that you'd NEVER use, but is intended to just grab a customer's attention as they walk by. Being pushed so far outside of their efficiency sweet spot just to get that extra 5% to "win benchmarks", when outside of specific use cases (and even if you actually need that 5%!) you're just consuming 50-100% more electricity for utterly marginal gains. What a waste of resources! All so children (or people who still act like them) can feel better about a purchase as they argue on the internet over nothing worth arguing about.

lukaesch 4y ago

Wouldn’t this mean that we should focus on writing more efficient code than before? Especially in the startup space I saw companies building software with the hypothesis “users need the latest device for our product and they will get faster anyway so we don’t need optimize our code. Instead we deliver features on max speed skipping optimizations and wait until our users upgraded to newer devices during the coming 2-4 years”.

mildmotive 4y ago
It’s offloading the cost to the customer. It is way cheaper to develop in some famous interpreted language than creating a set of robust compiled binaries. As long as customers can pay up for newer hardware we will keep seeing clunky UIs that can barely handle 20 list items of variable size without noticeable lag on a modern computer. I don’t even blame the companies for doing this. The benefit to cost ratio of using idk C++ for everything is just too bad.
- Ma8ee 4y ago
  But the inefficiencies you sometimes see today can’t even be explained with any bad choice of language. You can create more than fast enough programs with interpreted languages with garbage collection. But then of course you need to know at least a little bit about data structures and not doing dozens of REST calls anytime anyone taps the screen.
  - lpedrosa 4y ago
    What if doing dozens of REST calls is effectively the product?
    - Ma8ee 4y ago
      Could you explain? I’ve got a hard time imagining a user interested in the rest calls themselves.
  - mildmotive 4y ago

tapanjk 4y ago

> Obviously, given these data, volume is VERY important in business models that operate with high fixed and low variable costs. Off-topic but I wonder how much cheaper mobile phones would be if the manufacturers did not have to come up with a hardware design update every year or so? What if mobile phones were built to last longer, which would reduce the cost per phone due to high volume? Of course, I am not suggesting this is good for business but as a mere thought experiment.

alexvoda 4y ago
At this point the most direct and highest impact way of making phones last longer is forcing Qualcomm to support their chipsets for more than 2 years.

somat 4y ago

I am not convinced moore's law no longer holds true, consider that there is a third dimension that no one has yet figured out. I am no silicon engineer but I suspect a chip that fully takes advantage of the third dimension would be something like a sponge full of built in channels for the working fluid to remove heat. First however I suspect you will see chiplets arranged vertically like heatsink fins and the whole cpu would effectively be the water block, basically a vlsi version of the cray 3

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urthor 4y ago
https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/3DFabric.htm https://3dfabric.tsmc.com/english/dedicatedFoundry/technolog... What you're describing is called 3D stacking, and it works. It's just extraordinarily complex to resolve the intra-die latency issues, and many others, when going vertical. Hence expensive.
- petra 4y ago
  3D is already being used for ram/flash IC's. That's possible because most memory cells aren't being used in a memory chip - so heat density is reasonable. 3D is also used in AMD's 3D cache. But 3D logic on logic is more complicated because of heat issues. AFAIK there's no workable technical solution for that yet.
threatripper 4y ago
Heat removal is basically a 2D problem. A 3D pipe has a 2D cross section in which fluid can transport heat. Right now we are mostly limited by heat removal, so adding more height to the chip doesn't help anything with the heat. Also, the chips are already many layers thick and each layer means processing steps which means time and money. If you look into flash memory which aren't limited by heat, they have dozens of functional layers already and then we also stack those silicon wafers.

sitkack 4y ago

Cerebras' WFE is just a large chiplet.

BirAdam 4y ago

Unless I’m missing something, the article did mention Moore’s law proper with transistor density doubling every 18 months, but then meandered to talk about other things. M1 has 16 billion transistors thanks to TSMC. Each new node has delivered on Moore’s law with AMD and Apple. I don’t doubt that Moore’s law will stop. I can even say that it Moore’s law may have failed from time to time, but the spirit of the law lives. Moving to chiplets doesn’t change transistor density. This is a packaging feature and not a fabrication feature. This is done for manufacturing cost reduction and yield improvements.

wongarsu 4y ago
One interesting point is that even if Moore's law stops or slows down, chiplets allow us to increase transistor count independently of transistor density. Thus keeping alive the spirit of the law (processors get more and more transistors).
- bjourne 4y ago
  Maybe. How many times can you double the size of a 25mm^2 chip before it becomes impractically large?
  - WithinReason 4y ago
    Until you turn it into a 25mm^3 chip
urthor 4y ago
Moore's law is: Transistor density doubling every 18 months for a similar cost. https://t7m8e9c8.rocketcdn.me/wp-content/uploads/2020/09/precio-oblea-tsmc-5nm.jpg https://t7m8e9c8.rocketcdn.me/wp-content/uploads/2020/09/pre... https://en.wikipedia.org/wiki/Moore%27s_law#cite_note-Moore_1965-1 https://en.wikipedia.org/wiki/Moore%27s_law#cite_note-Moore_... By those terms, Moore's law is totally extinct. Folk haven't noticed however, because the "leading edge" logic manufacturers have 60% gross margins. The vast majority of their costs are in design, distribution and overhead. Price rises of 30% to 100% have disguised that the cost of manufacturing the silicon is an order of magnitude more than a decade ago. Granted, the above numbers are not the actual inflation adjusted wafer cost for leading edge nodes. But, $16,000 for a 300mm wafer is extraordinary.

PaulHoule 4y ago

Moore’s law is alive but the benefits are diminishing. Until 2005 or so, shrinking transistors automatically increased speed and reduced power consumption. When that ran out of steam, the industry went to multi core and massive parallelism with GPUs. Until recently each shrink also lowered the cost per transistor, but that seems to have run out also and has something to do with why Intel was stuck at 14nm for so long and why new GPU prices are so insane despite a collapse in demand and resolution of the supply chain crisis for high end chips. Chiplets at best are neutral with regard to cost. If manufacturing overhead is low, two chiplets give you twice the transistors at twice the cost. The industry did not pursue chiplets with a lot of vigor until now because it was a less competitive approach to scaling than shrinking transistors until now.

bjourne 4y ago
The reason Intel was "stuck" at 14 nm was because it took Extreme ultraviolet lithography (EUV) many years longer to become viable than was predicted. Prices may have more to do with the EUV market being dominated by ASML which has serious trouble producing lithography machines fast enough to meet demand.
- PaulHoule 4y ago
  If it’s not one thing it’s another. If progress continues then they will need some other expensive machine. Either that or they’ll try to stretch the life of EUV the same way Intel tried to delay EUV with extreme multiple patterning. It seems to me though that the ASML machines ought to get some competition from something more like a free electron laser.
- adrian_b 4y ago
  No, Intel was "stuck" at 14 nm because they believed that they will succeed to scale down the transistor sizes a lot more, without using EUV, as Pat Gelsinger has just explained in a long interview in the Verge. However they failed to implement with good results the methods that they had hoped to work, while the others, i.e. TSMC and Samsung had much more realistic roadmaps, which added EUV at the right moment. Intel was not stalled by waiting for EUV, on the contrary they were not prepared for the transition that was necessary when EUV was eventually ready. https://www.theverge.com/2022/10/4/23385652/pat-gelsinger-intel-chips-act-ohio-manufacturing-chip-shortage https://www.theverge.com/2022/10/4/23385652/pat-gelsinger-in...

Qem 4y ago

At least Proebsting's Law doesn't look so depressing anymore, by comparison: https://proebsting.cs.arizona.edu/law.html https://proebsting.cs.arizona.edu/law.html

WithinReason 4y ago

The number of people predicting the end of Moore's Law doubles every 2 years

ilaksh 4y ago

The history of computing is moving from one paradigm to another. We are well past the fast speedups in single thread transistor-based performance phase and into the hyper-parallelization phase. 3d stacking is another innovation that can help. But I think within a decade or two there will be a move away from silicon-only transistors to something like memristors or some type of optical or optoelectronic system that hasn't even been invented yet. This will provide some iterations with again radical parallel interconnect and quite possibly single thread speedups.

chatterhead 4y ago

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