19 ms·

NASA selects SiFive and makes RISC-V the go-to ecosystem for future missions

792 points by georgelyon 4y ago

inamberclad 4y ago
I'm ready to throw our old, expensive, and fairly slow flight computers with no drivers and terrible lead time to the curb and get on board with something new. Especially if an open ISA means that our systems will be more portable and faster to develop.
- smoldesu 4y ago
  It really seems like the perfect storm. Hopefully other folks like NASA will get comfortable jumping on the RISC train now that their only option isn't licensing from ARM.
  - giantrobot 4y ago
    NASA's been on the RISC train for nearly 30 years. They've been using the RAD750 since the turn of the century. Before the RAD750 they used the RAD6000, a radiation hardened POWER1 chip. They also use the Mongoose rad hard MIPS chips in a number of orbiters.
    - cestith 4y ago
      I have a document on my bookshelf a few feet from here comparing the 386 to the 486 for space mission purposes. Its core conclusion was that the 486 on-die cache was not spaceworthy and that with it disabled integer math was not really faster than on the 386. The recommendation was to use the 386+387+plus an external cache, partly because compilers for the 486 all optimized for that internal cache and compiled code poorly with it disabled, even if adding external cache. Putting computers in space is not a simple thing, of course. Such documents as this point out some of the difficulties. "Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System" Yuan-Kwai Liu NASA May, 1991 RTOP 488-51-01 ISBN 9781729173374 https://www.libreriauniversitaria.it/analysis-intel-386-and-i486/book/9781729173374 https://www.libreriauniversitaria.it/analysis-intel-386-and-...
      - giantrobot 4y ago
        That's interesting as the ISS (née Freedom) did in fact go with rad hard 386s for the MDMs (multiplexer-demultiplexer). These are the general purpose computers that connect dumb devices on the station like sensors or actuators to the station's main data bus. As for why Freedom/ISS went with 386s for the MDMs, I don't personally know. I'd guess that of the rad hard chips various defense companies shipped, a 386 was one of the more powerful. AFAIK the likes of the hardened RCA 1802 and some other 8-bit CPUs were pretty popular in the defense space. The RCA 1802 was used on a lot of the NASA's New Frontiers program probes. The MDM design on Freedom/ISS was meant to have a standardized component that was easily replaceable and use software to define the role of the device. An MDM plugged into a pump actuator today could have its EEPROM flashed and be plugged into a pressure sensor tomorrow. A useful feature in a system humans live in. That doesn't change the fact NASA's been RISC-y with their probes for the past three decades. The added power of the CPU (whatever the architecture) in today's probes means fewer specialized chips like were needed in older probes. That means more of the mass budget can go to science instruments and software can do the jobs that used to require dedicated chips. For anyone interested you can get the paper from NASA here[0]. It's pretty interesting. Thanks for pointing it out. [0] https://ntrs.nasa.gov/citations/19910016373 https://ntrs.nasa.gov/citations/19910016373
- gumby 4y ago
  There are already companies building hardware and software stacks so you can concentrate on the part you care about. I think this is great! Also excited to see RISC V gaining some acceptance in space.
- SassyThrowaway 4y ago
  > Especially if an open ISA means that our systems will be more portable and faster to develop. So I understand that RISC-V does not immediately impose licensing fees, but how does that translate into portability and speed of development? I'd think that tools and toolchains do not especially benefit from there not being licensing fees, and do benefit from somebody paying cool kernel/compiler hackers. Tools hardware designers use as well as the designs themselves will stay closed. What am I missing?
garblegarble 4y ago
The article (nor the product page for the X280) doesn't say whether these chips are radiation hardened, or whether NASA is now more comfortable with software solutions to the difficulties of reliable computation in space. If the latter, that seems (to a layperson) quite exciting, since more local processing capabilities will hopefully lead to more efficient use of the very limited radio bandwidth these missions have available at such vast distances.
- qbasic_forever 4y ago
  The last mars rover and its drone run embedded Linux, the JWST runs javascript (not node.js though!). NASA is already working with much more powerful and capable software stacks.
  - deelowe 4y ago
    > the JWST runs javascript What?! I'd like to know more about this. Does it have GC? I just can't fathom that being the case...
    - lifthrasiir 4y ago
      See [1] (HN discussion: [2]). According to the paper [3] it looks like that it does have a GC and its resource usage is limited by other means. [1] https://www.theverge.com/2022/8/18/23206110/james-webb-space-telescope-javascript-jwst-instrument-control https://www.theverge.com/2022/8/18/23206110/james-webb-space... [2] https://news.ycombinator.com/item?id=32519918 https://news.ycombinator.com/item?id=32519918 [3] https://www.jwst.nasa.gov/resources/ISIMmanuscript.pdf#page=17 https://www.jwst.nasa.gov/resources/ISIMmanuscript.pdf#page=...
      - acchow 4y ago
        > If you’re still worried, do note that the Space Telescope Science Institute’s document mentions that the script processor itself is written in C++ So they decided on Javascript back in 2006 and it uses an interpreter/runtime written in C++. Which runtime is this?
tibbydudeza 4y ago
Interestingly SiFive RISC V core was licensed by Tenstorrent (Jim Keller AI startup) for their designs.
- FullyFunctional 4y ago
  True but know also that Tenstorrent is working on their own superscalar OoO chip as well.
  - tibbydudeza 4y ago
    They probably need a "director" CPU with a familiar programming interface to orchestrate their AI engines ???.
    - snvzz 4y ago
      They're apparently working on one, in-house[0]. It's apparently called Ascalon, and there's some information starting at around 8 minutes into the video. 0. https://youtu.be/KOHQQyAKY14 https://youtu.be/KOHQQyAKY14
      - tibbydudeza 4y ago
        Shot.
        snvzz 4y ago
        Yes, and it is a RISC-V core by a team led by Jim Keller.
neilv 4y ago
It's great to see parts of the US government embracing RISC-V and SiFive. I hope NASA and others using RISC-V also take the opportunity, of a bit of a fresh start, to push for more of an open hardware platform around the CPUs (chipsets, devices, etc.).
- 1-6 4y ago
  I hope that’s the intention. Silicon Valley pretty much sprouted with military funding. Unfortunately, projects with long lead times are impossible to sustain in this new economy and research scientists will get scouted before NASA gets to increase their pay.
temptemptemp111 4y ago
gchadwick 4y ago
I am a little surprised to see this. I'd imagine NASA would chose a CPU with an already proven track record (especially for something so wide ranging, the press release says it expected to be used for 'virtually every future space mission, from planetary exploration to lunar and Mars surface missions'. This is a new design from SiFive and there's not a huge amount of SiFive IP around yet to demonstrate how good (or otherwise) their verification is. Running into a hardware bug whilst your CPU is in space is not good. Still good SiFive have convinced NASA otherwise, they must have a pretty strong verification story behind the scenes.
- pinewurst 4y ago
  NASA is partitioned between the (IMHO limited) parts that actually do stuff and the golly-geewhiz-PR stuff. People who are planning next gen planetary missions are considering trusted, proven rad hard platforms. This is just PR to distract in its own small way from the SLS debacle.
  - permalac 4y ago
    What debacle? Is it dead?
    - pinewurst 4y ago
      Money spent vs results over time. Results excluding Boeing & subcontractor revenue. SLS was originally sold as cost effective reuse of existing SSMEs combined with relatively simple tankage to get a cheap large booster. Against those metrics it’s a debacle, unclear if it ever will fly, especially more than once.
      - mjevans 4y ago
        While I agree about SLS, and I'm also hopeful about SpaceX's Starship stack, I'd really like to see a successful test. They're working on it, but just imagine how much closer they could have been with even a fraction of this SLS boondoggle contributed. If NASA is supposed to be a multi-state grant to the sciences, I'd much rather they focus the funding where it will deliver results that benefit the public commons. The jobs program for obsolete and finicky space tech is a dis-service to the public and even the workers who's skills are in questionably useful specialties.
morcheeba 4y ago
Interesting! ESA has been using a custom SPARC V8 rad hard architecture: https://en.wikipedia.org/wiki/LEON https://en.wikipedia.org/wiki/LEON I'm currently using a dual-core 90 MHz processor that is relatively advanced and has good performance for many applications. It has error-correcting memories (SDRAM, cache, registers) and a lot of integrated peripherals (spacewire, serial, ethernet, 1553, CCSDS) that help reduce board complexity. Next up in the pipeline is an 8-core 1 GHz monster: https://www.gaisler.com/index.php/products/components/gr765 https://www.gaisler.com/index.php/products/components/gr765
- pkaye 4y ago
  NASA has mostly been using a PowerPC. https://en.wikipedia.org/wiki/RAD750 https://en.wikipedia.org/wiki/RAD750
  - deleted 4y ago
    [deleted]
- shrubble 4y ago
  Are any of these boards available for regular people at a regular person kind of price? Or is it 1000s of USD for an evaluation board?
  - techdragon 4y ago
    It’s super hard to get pricing info for radiation hardened chips that are currently being sold, let alone just buying one from Digi-Key. It’s pretty damn annoying if you just want the one super robust chip for a system supervisor or something else like that, to have no idea how to plan the design for a cost budget before you begin doing a lot of contact work talking to people for price quotes. It’s a weird ecosystem that feels surprising antiquated compared to the more modern parts of the embedded ecosystem that I’m familiar with. Worst price I can remember off hand was $15 grand USD for a radiation hardened microcontroller, pretty sure it was an Arduino mega family chip I could have gotten the industrial quality version of for $25 bucks from Digi-Key… if I didn’t want it radiation hardened.
vaxman 4y ago
RISC-V is NASA bad? “Launch aborted, whenever we access the pressurization control we’re getting an ‘ISA not implemented in this version of the core’ error from the controller that arrived overnight. They must have received the wrong version of the chip and didn’t catch it in the test rig we gave them 6 years ago.” #roflmao
sylware 4y ago
Write once assembly with a simple macro-assembler, run "everywhere"...
UltraViolence 4y ago
I wonder if NASA has a clue that RISC-V's ISA is open-source but SiFive's designs certainly aren't.
- deleted 4y ago
  [deleted]
- Jtsummers 4y ago
  You can't launch an ISA into space and expect it to do anything. At some point, hardware has to be designed and built based on that ISA.
  - babypuncher 4y ago
    Nonsense; I printed out a copy of the AGC instruction set reference, stuffed it in one of my model rockets, and it turned into a Saturn V mid-flight.
  - UltraViolence 4y ago
    Then what advantage does it have over ARM or x64? The ISA being open doesn't seem to make any difference at all.
    - brucehoult 4y ago
      RISC-V is massively simpler (and smaller silicon and lower energy use) for the same performance. Oh, and significantly smaller code size too, so everything from ROMs to RAM (if code is loaded to RAM) to icache can be sized smaller. The ISA being open source means that if SiFive goes out of business or changes its product lineup, or starts to make buggy stuff, or charge too much ... no matter what happens, the customer is free to find another vendor to make software-compatible chips. As we've found out with ARM this week, even if one company with ARM's highest and most expensive form of license, the Architecture License Agreement (ALA), makes a CPU design they are not allowed to transfer or sell that design to another company that also has an ALA without ARM's explicit permission. Or so ARM claims. Let's see what the courts decide about that.
jakedata 4y ago
I'd love to see an implementation in silicon carbide so we could drop it on Venus, wait for it to bounce a few times and then start exploring. https://spectrum.ieee.org/the-radio-we-could-send-to-hell https://spectrum.ieee.org/the-radio-we-could-send-to-hell
- babypuncher 4y ago
  I always wondered why NASA never sent any surface probes to Venus, until I read about the insane engineering (and lots of trial and error) that went into the Soviet Union's Venera program. Despite all that effort, the successful Venera probes only lasted minutes on the surface before failing.
  - giantrobot 4y ago
    The fact a lander is only going to return an hour (at best) of science data is why NASA hasn't bothered with Venus. There's a low chance of initial success and then no real opportunity for a mission extension if things actually go well. A Mars lander returns a lot more science per dollar than a Venus lander will.
    - jakedata 4y ago
      I think a larger mission with some sort of airship dropping little science packages would yield quite a trove of data without the entire mission burning up in an hour. Hopefully the success of the little Martian helicopter gives mission planners something to think about. -edited to add, something like a molten salt battery could travel to Venus completely inert and only become active as it warms, also acting as a heat sink.
      - deleted 4y ago
        [deleted]
    - mturmon 4y ago
      The DAVINCI upcoming Venus mission (2031) has a descent stage, but surface operations are not part of the prime mission. Just taking pictures and readings on gas composition as it goes down towards the surface https://www.nasa.gov/feature/goddard/2022/nasa-s-davinci-mission-to-take-the-plunge-through-massive-atmosphere-of-venus https://www.nasa.gov/feature/goddard/2022/nasa-s-davinci-mis... > “The probe will touch-down in the Alpha Regio mountains but is not required to operate once it lands, as all of the required science data will be taken before reaching the surface.” said Stephanie Getty, deputy principal investigator from Goddard. “If we survive the touchdown at about 25 miles per hour (12 meters/second), we could have up to 17-18 minutes of operations on the surface under ideal conditions.” There will be a companion orbiter, as well, called VERITAS: https://www.jpl.nasa.gov/missions/veritas https://www.jpl.nasa.gov/missions/veritas
jvanderbot 4y ago
For context: "This contract is part of NASA’s High-Performance Space Computing project". I used to work with the HPSC leads and paid attention to it. This is one of many parallel threads for next-gen computing, including snapdragon and others. Yes, it will be rad-hard. That was a program requirement and is mentioned in the press release. As such, it fits a particular mission profile. There is no existing compulsion for missions to use HPSC. This is a technology development program seeking to meet the requirements of missions. It's great news they converged on an architecture! As part of their development, HPSC folks will seek mission partners for tech demos. Then, missions will voluntarily (or with some light compulsion) adopt the technology based on the growing heritage and mission need.
- aidenn0 4y ago
  Radiation hardened targets seem to stay around for a long time, judging by how many 750s are still around, so I suspect we'll see RISC-V around in aerospace for quite some time
- ncmncm 4y ago
  This is really pretty strange. RISC-V is a respectable enough architecture, but not better than recent POWER designs, equally open. NASA has an enormous amount of experience with POWER. I suppose it comes down to what bidders are offering to build for them.
  - justahuman74 4y ago
    Sometimes there are documents that say why NASA chose what they chose, there might be one for this
    - theteapot 4y ago
      Following article has a bit more info on motivations, although it's from SiFive guy not NASA directly -- https://www.theregister.com/2022/09/06/nasas_spaceflight_computer_risc_v/ https://www.theregister.com/2022/09/06/nasas_spaceflight_com.... Summary: more vibrant eco system over the next 5-20 years and vector math.
mattcaldwell 4y ago
RISC architecture is gonna change everything.
- tinktank 4y ago
  It already did.
- killingtime74 4y ago
  ARM is already RISC. Majority of smart phones in the world
- crotho 4y ago
- arcticbull 4y ago
  Basically all processors today are RISC. Event the venerable behemoth x86(_64) has a front-end which translates CISC instructions into RISC-like micro-ops. The distinction is pretty meaningless today.
  - snvzz 4y ago
    Micro-ops are a microarchitecture implementation detail. They are also used by many RISC microarchitectures, and are ultimately irrelevant to ISA. Ever since the RISC paper, every new architecture of any remaining significance today has been RISC. Today, it makes more sense than ever[0]. The only CISC that remains in large-scale use is x86, which I expect to finally be deprecated during this decade. 0. https://itnext.io/risc-vs-cisc-microprocessor-philosophy-in-2022-fa871861bc94 https://itnext.io/risc-vs-cisc-microprocessor-philosophy-in-...
    - deleted 4y ago
      [deleted]
    - arcticbull 4y ago
      My point was more that 'RISC vs CISC' is not a useful way to compare two processors. In the same way CISC CPUs break down instructions into a series of micro-ops, RISC CPUs (like the RISC-V) fuse instructions into macro-ops. Yes the ISA is different and yes that imposes some constraints on the design but it's not a particularly useful way of comparing two processors. Ok CISC ISAs are out of favor today, although I suspect as some of these RISC ISAs age, they'll accrete instructions. The ARM ISA sure is a lot chonkier than it used to be. Modern ARM CPUs have a massive micro-op cache just like x86 CPUs do. I wouldn't be surprised if we wake up one day and it's half way to x86. In my opinion ISA isn't relevant or interesting. [1] I echo the sentiments in this article: > In short, there’s no meaningful difference between RISC/ARM and CISC/x86 as far as performance is concerned. What matters is keeping the core fed, and fed with the right data which puts focus on cache design, branch prediction, prefetching, and a variety of cool tricks like predicting whether a load can execute before a store to an unknown address. So to your point that: > Today, [RISC] makes more sense than ever. I would respond, today, it makes less difference than ever. What actually happens under the hood of a modern performance-optimized CPU is so far removed from the ISA that the ISA is just a design curiosity. 'RISC architecture' isn't going to 'change everything' - how it's implemented: advances in branch prediction, prefetching, etc - that's going to continue to iteratively improve processors. The number of instructions is truly not a factor of note. Does it never matter? Probably sometimes. Once in a while in some very specific applications - like pico-amp scale microcontrollers - it might? But for anything you’re thinking of it’s super irrelevant. [1] https://chipsandcheese.com/2021/07/13/arm-or-x86-isa-doesnt-matter/ https://chipsandcheese.com/2021/07/13/arm-or-x86-isa-doesnt-...
keepquestioning 4y ago
Guess its time to learn RISC-V. Any good courses?
- Aperocky 4y ago
  Unless you're into compilers and whatnot, it shouldn't be necessary?
  - keepquestioning 4y ago
    You need it for OS or RTOS design
- brucehoult 4y ago
  If you already understand assembly-language programming for some other ISA then you'll have no trouble following straight from the RISC-V reference manual: https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf https://github.com/riscv/riscv-isa-manual/releases/download/... Plus recently ratified extensions: https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions https://wiki.riscv.org/display/HOME/Recently+Ratified+Extens...
BryLuc 4y ago
RockingGoodNite 4y ago
I wonder if NASA would be interested in my 1980 Timex Sinclair 1000?
- krallja 4y ago
  Why, is there an RFP for doorstops?
  - RockingGoodNite 4y ago
    RISC-V wasn't that bad. Lol. /s
kfihihc 4y ago
StarFive announces new JH7110 SoC and SBC based on SiFive U74 CPU core[1]. You can experience SiFive's product in the real world. [1]: https://www.kickstarter.com/projects/starfive/visionfive-2 https://www.kickstarter.com/projects/starfive/visionfive-2
- preisschild 4y ago
  Pine64 is also releasing their own JH7110-based SBC soon[1]. Antmicro also teased their low-density SoM board [2] last year, but I have not heard any news about that since, which is a shame because you could put a ton of those in a server rack. [1]: https://www.cnx-software.com/2022/08/29/pine64-star64-sbc-starfive-jh7110-quad-core-risc-v-processor-imagination-gpu/ https://www.cnx-software.com/2022/08/29/pine64-star64-sbc-st... [2]: https://www.cnx-software.com/2021/04/30/antmicro-arvsom-offers-starfive-71x0-risc-v-processor-raspberry-pi-cm4-compatibility/ https://www.cnx-software.com/2021/04/30/antmicro-arvsom-offe...
amelius 4y ago
Glad they are not sending entire M1 MacBooks into space for lack of individual M1 silicon modules.
gjadi 4y ago
What is "ratification intelligence"? From the article: > The HPSC processor and X280 compute subsystem is expected to be useful to other government agencies in a variety of applications including industrial automation, edge computing, ratification intelligence, and aerospace applications. I couldn't find a good answer online.
- cestith 4y ago
  I couldn't find a formal definition quickly from my sources. However, it appears in context in a few places and it seems to use the sense of "ratify" meaning "to confirm" or "to validate". "Ratify" and "ratification" are used in places where one might expect to replace it in the prose with "verify" or "verification", as in using multiple different intelligence sources (video, photo, signals, live, etc) to build confirmatory evidence of something when multiple overlapping sources exist rather than trusting a single source.
  - sheepybloke 4y ago
    A chip like that could be used for sensor fusion and validation, calculation validation, and a lot of other things. For example, if you have three IMUs doing your positioning, you could use this to ratify and validate that they are all working correctly or throw out an answer if one disagrees with the other. I've generally thought of using an FPGA for this sort of work, but a certified and inexpensive coprocessor would work well for this use case.
  - gjadi 4y ago
    Ok, so that's related to consensus algorithm. Thank you!

792 points by georgelyon 4y ago

I'm ready to throw our old, expensive, and fairly slow flight computers with no drivers and terrible lead time to the curb and get on board with something new. Especially if an open ISA means that our systems will be more portable and faster to develop.

smoldesu 4y ago
It really seems like the perfect storm. Hopefully other folks like NASA will get comfortable jumping on the RISC train now that their only option isn't licensing from ARM.
- giantrobot 4y ago
  NASA's been on the RISC train for nearly 30 years. They've been using the RAD750 since the turn of the century. Before the RAD750 they used the RAD6000, a radiation hardened POWER1 chip. They also use the Mongoose rad hard MIPS chips in a number of orbiters.
  - cestith 4y ago
    I have a document on my bookshelf a few feet from here comparing the 386 to the 486 for space mission purposes. Its core conclusion was that the 486 on-die cache was not spaceworthy and that with it disabled integer math was not really faster than on the 386. The recommendation was to use the 386+387+plus an external cache, partly because compilers for the 486 all optimized for that internal cache and compiled code poorly with it disabled, even if adding external cache. Putting computers in space is not a simple thing, of course. Such documents as this point out some of the difficulties. "Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System" Yuan-Kwai Liu NASA May, 1991 RTOP 488-51-01 ISBN 9781729173374 https://www.libreriauniversitaria.it/analysis-intel-386-and-i486/book/9781729173374 https://www.libreriauniversitaria.it/analysis-intel-386-and-...
    - giantrobot 4y ago
      That's interesting as the ISS (née Freedom) did in fact go with rad hard 386s for the MDMs (multiplexer-demultiplexer). These are the general purpose computers that connect dumb devices on the station like sensors or actuators to the station's main data bus. As for why Freedom/ISS went with 386s for the MDMs, I don't personally know. I'd guess that of the rad hard chips various defense companies shipped, a 386 was one of the more powerful. AFAIK the likes of the hardened RCA 1802 and some other 8-bit CPUs were pretty popular in the defense space. The RCA 1802 was used on a lot of the NASA's New Frontiers program probes. The MDM design on Freedom/ISS was meant to have a standardized component that was easily replaceable and use software to define the role of the device. An MDM plugged into a pump actuator today could have its EEPROM flashed and be plugged into a pressure sensor tomorrow. A useful feature in a system humans live in. That doesn't change the fact NASA's been RISC-y with their probes for the past three decades. The added power of the CPU (whatever the architecture) in today's probes means fewer specialized chips like were needed in older probes. That means more of the mass budget can go to science instruments and software can do the jobs that used to require dedicated chips. For anyone interested you can get the paper from NASA here[0]. It's pretty interesting. Thanks for pointing it out. [0] https://ntrs.nasa.gov/citations/19910016373 https://ntrs.nasa.gov/citations/19910016373
gumby 4y ago
There are already companies building hardware and software stacks so you can concentrate on the part you care about. I think this is great! Also excited to see RISC V gaining some acceptance in space.
SassyThrowaway 4y ago
> Especially if an open ISA means that our systems will be more portable and faster to develop. So I understand that RISC-V does not immediately impose licensing fees, but how does that translate into portability and speed of development? I'd think that tools and toolchains do not especially benefit from there not being licensing fees, and do benefit from somebody paying cool kernel/compiler hackers. Tools hardware designers use as well as the designs themselves will stay closed. What am I missing?

garblegarble 4y ago

The article (nor the product page for the X280) doesn't say whether these chips are radiation hardened, or whether NASA is now more comfortable with software solutions to the difficulties of reliable computation in space. If the latter, that seems (to a layperson) quite exciting, since more local processing capabilities will hopefully lead to more efficient use of the very limited radio bandwidth these missions have available at such vast distances.

qbasic_forever 4y ago
The last mars rover and its drone run embedded Linux, the JWST runs javascript (not node.js though!). NASA is already working with much more powerful and capable software stacks.
- deelowe 4y ago
  > the JWST runs javascript What?! I'd like to know more about this. Does it have GC? I just can't fathom that being the case...
  - lifthrasiir 4y ago
    See [1] (HN discussion: [2]). According to the paper [3] it looks like that it does have a GC and its resource usage is limited by other means. [1] https://www.theverge.com/2022/8/18/23206110/james-webb-space-telescope-javascript-jwst-instrument-control https://www.theverge.com/2022/8/18/23206110/james-webb-space... [2] https://news.ycombinator.com/item?id=32519918 https://news.ycombinator.com/item?id=32519918 [3] https://www.jwst.nasa.gov/resources/ISIMmanuscript.pdf#page=17 https://www.jwst.nasa.gov/resources/ISIMmanuscript.pdf#page=...
    - acchow 4y ago
      > If you’re still worried, do note that the Space Telescope Science Institute’s document mentions that the script processor itself is written in C++ So they decided on Javascript back in 2006 and it uses an interpreter/runtime written in C++. Which runtime is this?

tibbydudeza 4y ago

Interestingly SiFive RISC V core was licensed by Tenstorrent (Jim Keller AI startup) for their designs.

FullyFunctional 4y ago
True but know also that Tenstorrent is working on their own superscalar OoO chip as well.
- tibbydudeza 4y ago
  They probably need a "director" CPU with a familiar programming interface to orchestrate their AI engines ???.
  - snvzz 4y ago
    They're apparently working on one, in-house[0]. It's apparently called Ascalon, and there's some information starting at around 8 minutes into the video. 0. https://youtu.be/KOHQQyAKY14 https://youtu.be/KOHQQyAKY14
    - tibbydudeza 4y ago
      Shot.
      - snvzz 4y ago
        Yes, and it is a RISC-V core by a team led by Jim Keller.

neilv 4y ago

It's great to see parts of the US government embracing RISC-V and SiFive. I hope NASA and others using RISC-V also take the opportunity, of a bit of a fresh start, to push for more of an open hardware platform around the CPUs (chipsets, devices, etc.).

1-6 4y ago
I hope that’s the intention. Silicon Valley pretty much sprouted with military funding. Unfortunately, projects with long lead times are impossible to sustain in this new economy and research scientists will get scouted before NASA gets to increase their pay.

temptemptemp111 4y ago

gchadwick 4y ago

I am a little surprised to see this. I'd imagine NASA would chose a CPU with an already proven track record (especially for something so wide ranging, the press release says it expected to be used for 'virtually every future space mission, from planetary exploration to lunar and Mars surface missions'. This is a new design from SiFive and there's not a huge amount of SiFive IP around yet to demonstrate how good (or otherwise) their verification is. Running into a hardware bug whilst your CPU is in space is not good. Still good SiFive have convinced NASA otherwise, they must have a pretty strong verification story behind the scenes.

pinewurst 4y ago
NASA is partitioned between the (IMHO limited) parts that actually do stuff and the golly-geewhiz-PR stuff. People who are planning next gen planetary missions are considering trusted, proven rad hard platforms. This is just PR to distract in its own small way from the SLS debacle.
- permalac 4y ago
  What debacle? Is it dead?
  - pinewurst 4y ago
    Money spent vs results over time. Results excluding Boeing & subcontractor revenue. SLS was originally sold as cost effective reuse of existing SSMEs combined with relatively simple tankage to get a cheap large booster. Against those metrics it’s a debacle, unclear if it ever will fly, especially more than once.
    - mjevans 4y ago
      While I agree about SLS, and I'm also hopeful about SpaceX's Starship stack, I'd really like to see a successful test. They're working on it, but just imagine how much closer they could have been with even a fraction of this SLS boondoggle contributed. If NASA is supposed to be a multi-state grant to the sciences, I'd much rather they focus the funding where it will deliver results that benefit the public commons. The jobs program for obsolete and finicky space tech is a dis-service to the public and even the workers who's skills are in questionably useful specialties.

morcheeba 4y ago

Interesting! ESA has been using a custom SPARC V8 rad hard architecture: https://en.wikipedia.org/wiki/LEON https://en.wikipedia.org/wiki/LEON I'm currently using a dual-core 90 MHz processor that is relatively advanced and has good performance for many applications. It has error-correcting memories (SDRAM, cache, registers) and a lot of integrated peripherals (spacewire, serial, ethernet, 1553, CCSDS) that help reduce board complexity. Next up in the pipeline is an 8-core 1 GHz monster: https://www.gaisler.com/index.php/products/components/gr765 https://www.gaisler.com/index.php/products/components/gr765

pkaye 4y ago
NASA has mostly been using a PowerPC. https://en.wikipedia.org/wiki/RAD750 https://en.wikipedia.org/wiki/RAD750
- deleted 4y ago
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shrubble 4y ago
Are any of these boards available for regular people at a regular person kind of price? Or is it 1000s of USD for an evaluation board?
- techdragon 4y ago
  It’s super hard to get pricing info for radiation hardened chips that are currently being sold, let alone just buying one from Digi-Key. It’s pretty damn annoying if you just want the one super robust chip for a system supervisor or something else like that, to have no idea how to plan the design for a cost budget before you begin doing a lot of contact work talking to people for price quotes. It’s a weird ecosystem that feels surprising antiquated compared to the more modern parts of the embedded ecosystem that I’m familiar with. Worst price I can remember off hand was $15 grand USD for a radiation hardened microcontroller, pretty sure it was an Arduino mega family chip I could have gotten the industrial quality version of for $25 bucks from Digi-Key… if I didn’t want it radiation hardened.

vaxman 4y ago

RISC-V is NASA bad? “Launch aborted, whenever we access the pressurization control we’re getting an ‘ISA not implemented in this version of the core’ error from the controller that arrived overnight. They must have received the wrong version of the chip and didn’t catch it in the test rig we gave them 6 years ago.” #roflmao

sylware 4y ago

Write once assembly with a simple macro-assembler, run "everywhere"...

UltraViolence 4y ago

I wonder if NASA has a clue that RISC-V's ISA is open-source but SiFive's designs certainly aren't.

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Jtsummers 4y ago
You can't launch an ISA into space and expect it to do anything. At some point, hardware has to be designed and built based on that ISA.
- babypuncher 4y ago
  Nonsense; I printed out a copy of the AGC instruction set reference, stuffed it in one of my model rockets, and it turned into a Saturn V mid-flight.
- UltraViolence 4y ago
  Then what advantage does it have over ARM or x64? The ISA being open doesn't seem to make any difference at all.
  - brucehoult 4y ago
    RISC-V is massively simpler (and smaller silicon and lower energy use) for the same performance. Oh, and significantly smaller code size too, so everything from ROMs to RAM (if code is loaded to RAM) to icache can be sized smaller. The ISA being open source means that if SiFive goes out of business or changes its product lineup, or starts to make buggy stuff, or charge too much ... no matter what happens, the customer is free to find another vendor to make software-compatible chips. As we've found out with ARM this week, even if one company with ARM's highest and most expensive form of license, the Architecture License Agreement (ALA), makes a CPU design they are not allowed to transfer or sell that design to another company that also has an ALA without ARM's explicit permission. Or so ARM claims. Let's see what the courts decide about that.

jakedata 4y ago

I'd love to see an implementation in silicon carbide so we could drop it on Venus, wait for it to bounce a few times and then start exploring. https://spectrum.ieee.org/the-radio-we-could-send-to-hell https://spectrum.ieee.org/the-radio-we-could-send-to-hell

babypuncher 4y ago
I always wondered why NASA never sent any surface probes to Venus, until I read about the insane engineering (and lots of trial and error) that went into the Soviet Union's Venera program. Despite all that effort, the successful Venera probes only lasted minutes on the surface before failing.
- giantrobot 4y ago
  The fact a lander is only going to return an hour (at best) of science data is why NASA hasn't bothered with Venus. There's a low chance of initial success and then no real opportunity for a mission extension if things actually go well. A Mars lander returns a lot more science per dollar than a Venus lander will.
  - jakedata 4y ago
    I think a larger mission with some sort of airship dropping little science packages would yield quite a trove of data without the entire mission burning up in an hour. Hopefully the success of the little Martian helicopter gives mission planners something to think about. -edited to add, something like a molten salt battery could travel to Venus completely inert and only become active as it warms, also acting as a heat sink.
    - deleted 4y ago
      [deleted]
  - mturmon 4y ago
    The DAVINCI upcoming Venus mission (2031) has a descent stage, but surface operations are not part of the prime mission. Just taking pictures and readings on gas composition as it goes down towards the surface https://www.nasa.gov/feature/goddard/2022/nasa-s-davinci-mission-to-take-the-plunge-through-massive-atmosphere-of-venus https://www.nasa.gov/feature/goddard/2022/nasa-s-davinci-mis... > “The probe will touch-down in the Alpha Regio mountains but is not required to operate once it lands, as all of the required science data will be taken before reaching the surface.” said Stephanie Getty, deputy principal investigator from Goddard. “If we survive the touchdown at about 25 miles per hour (12 meters/second), we could have up to 17-18 minutes of operations on the surface under ideal conditions.” There will be a companion orbiter, as well, called VERITAS: https://www.jpl.nasa.gov/missions/veritas https://www.jpl.nasa.gov/missions/veritas

jvanderbot 4y ago

For context: "This contract is part of NASA’s High-Performance Space Computing project". I used to work with the HPSC leads and paid attention to it. This is one of many parallel threads for next-gen computing, including snapdragon and others. Yes, it will be rad-hard. That was a program requirement and is mentioned in the press release. As such, it fits a particular mission profile. There is no existing compulsion for missions to use HPSC. This is a technology development program seeking to meet the requirements of missions. It's great news they converged on an architecture! As part of their development, HPSC folks will seek mission partners for tech demos. Then, missions will voluntarily (or with some light compulsion) adopt the technology based on the growing heritage and mission need.

aidenn0 4y ago
Radiation hardened targets seem to stay around for a long time, judging by how many 750s are still around, so I suspect we'll see RISC-V around in aerospace for quite some time
ncmncm 4y ago
This is really pretty strange. RISC-V is a respectable enough architecture, but not better than recent POWER designs, equally open. NASA has an enormous amount of experience with POWER. I suppose it comes down to what bidders are offering to build for them.
- justahuman74 4y ago
  Sometimes there are documents that say why NASA chose what they chose, there might be one for this
  - theteapot 4y ago
    Following article has a bit more info on motivations, although it's from SiFive guy not NASA directly -- https://www.theregister.com/2022/09/06/nasas_spaceflight_computer_risc_v/ https://www.theregister.com/2022/09/06/nasas_spaceflight_com.... Summary: more vibrant eco system over the next 5-20 years and vector math.

mattcaldwell 4y ago

RISC architecture is gonna change everything.

tinktank 4y ago
It already did.
killingtime74 4y ago
ARM is already RISC. Majority of smart phones in the world
crotho 4y ago
arcticbull 4y ago
Basically all processors today are RISC. Event the venerable behemoth x86(_64) has a front-end which translates CISC instructions into RISC-like micro-ops. The distinction is pretty meaningless today.
- snvzz 4y ago
  Micro-ops are a microarchitecture implementation detail. They are also used by many RISC microarchitectures, and are ultimately irrelevant to ISA. Ever since the RISC paper, every new architecture of any remaining significance today has been RISC. Today, it makes more sense than ever[0]. The only CISC that remains in large-scale use is x86, which I expect to finally be deprecated during this decade. 0. https://itnext.io/risc-vs-cisc-microprocessor-philosophy-in-2022-fa871861bc94 https://itnext.io/risc-vs-cisc-microprocessor-philosophy-in-...
  - deleted 4y ago
    [deleted]
  - arcticbull 4y ago
    My point was more that 'RISC vs CISC' is not a useful way to compare two processors. In the same way CISC CPUs break down instructions into a series of micro-ops, RISC CPUs (like the RISC-V) fuse instructions into macro-ops. Yes the ISA is different and yes that imposes some constraints on the design but it's not a particularly useful way of comparing two processors. Ok CISC ISAs are out of favor today, although I suspect as some of these RISC ISAs age, they'll accrete instructions. The ARM ISA sure is a lot chonkier than it used to be. Modern ARM CPUs have a massive micro-op cache just like x86 CPUs do. I wouldn't be surprised if we wake up one day and it's half way to x86. In my opinion ISA isn't relevant or interesting. [1] I echo the sentiments in this article: > In short, there’s no meaningful difference between RISC/ARM and CISC/x86 as far as performance is concerned. What matters is keeping the core fed, and fed with the right data which puts focus on cache design, branch prediction, prefetching, and a variety of cool tricks like predicting whether a load can execute before a store to an unknown address. So to your point that: > Today, [RISC] makes more sense than ever. I would respond, today, it makes less difference than ever. What actually happens under the hood of a modern performance-optimized CPU is so far removed from the ISA that the ISA is just a design curiosity. 'RISC architecture' isn't going to 'change everything' - how it's implemented: advances in branch prediction, prefetching, etc - that's going to continue to iteratively improve processors. The number of instructions is truly not a factor of note. Does it never matter? Probably sometimes. Once in a while in some very specific applications - like pico-amp scale microcontrollers - it might? But for anything you’re thinking of it’s super irrelevant. [1] https://chipsandcheese.com/2021/07/13/arm-or-x86-isa-doesnt-matter/ https://chipsandcheese.com/2021/07/13/arm-or-x86-isa-doesnt-...

keepquestioning 4y ago

Guess its time to learn RISC-V. Any good courses?

Aperocky 4y ago
Unless you're into compilers and whatnot, it shouldn't be necessary?
- keepquestioning 4y ago
  You need it for OS or RTOS design
brucehoult 4y ago
If you already understand assembly-language programming for some other ISA then you'll have no trouble following straight from the RISC-V reference manual: https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf https://github.com/riscv/riscv-isa-manual/releases/download/... Plus recently ratified extensions: https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions https://wiki.riscv.org/display/HOME/Recently+Ratified+Extens...

BryLuc 4y ago

RockingGoodNite 4y ago

I wonder if NASA would be interested in my 1980 Timex Sinclair 1000?

krallja 4y ago
Why, is there an RFP for doorstops?
- RockingGoodNite 4y ago
  RISC-V wasn't that bad. Lol. /s

kfihihc 4y ago

StarFive announces new JH7110 SoC and SBC based on SiFive U74 CPU core[1]. You can experience SiFive's product in the real world. [1]: https://www.kickstarter.com/projects/starfive/visionfive-2 https://www.kickstarter.com/projects/starfive/visionfive-2

preisschild 4y ago
Pine64 is also releasing their own JH7110-based SBC soon[1]. Antmicro also teased their low-density SoM board [2] last year, but I have not heard any news about that since, which is a shame because you could put a ton of those in a server rack. [1]: https://www.cnx-software.com/2022/08/29/pine64-star64-sbc-starfive-jh7110-quad-core-risc-v-processor-imagination-gpu/ https://www.cnx-software.com/2022/08/29/pine64-star64-sbc-st... [2]: https://www.cnx-software.com/2021/04/30/antmicro-arvsom-offers-starfive-71x0-risc-v-processor-raspberry-pi-cm4-compatibility/ https://www.cnx-software.com/2021/04/30/antmicro-arvsom-offe...

amelius 4y ago

Glad they are not sending entire M1 MacBooks into space for lack of individual M1 silicon modules.

gjadi 4y ago

What is "ratification intelligence"? From the article: > The HPSC processor and X280 compute subsystem is expected to be useful to other government agencies in a variety of applications including industrial automation, edge computing, ratification intelligence, and aerospace applications. I couldn't find a good answer online.

cestith 4y ago
I couldn't find a formal definition quickly from my sources. However, it appears in context in a few places and it seems to use the sense of "ratify" meaning "to confirm" or "to validate". "Ratify" and "ratification" are used in places where one might expect to replace it in the prose with "verify" or "verification", as in using multiple different intelligence sources (video, photo, signals, live, etc) to build confirmatory evidence of something when multiple overlapping sources exist rather than trusting a single source.
- sheepybloke 4y ago
  A chip like that could be used for sensor fusion and validation, calculation validation, and a lot of other things. For example, if you have three IMUs doing your positioning, you could use this to ratify and validate that they are all working correctly or throw out an answer if one disagrees with the other. I've generally thought of using an FPGA for this sort of work, but a certified and inexpensive coprocessor would work well for this use case.
- gjadi 4y ago
  Ok, so that's related to consensus algorithm. Thank you!