53 ms·
The 100 MHz 6502
- Simplicitas 5y ago"The 65.02 MHz 6502" would be a much better headline
- marcodiego 5y ago> same footprint and pinout as the original 6502 I like this idea. This may bring a new level of repairability for devices whose chips will, one day, no longer be manufactured.
- coldacid 5y agoThis is often the first consideration after "does it match the behaviour of the original chip perfectly" when dealing with FPGA reimplementations of other chips.
- Lio 5y agoNice. This would be fun to add to an Acorn BBC or BBC Master via its Tube interface. https://en.wikipedia.org/wiki/Tube_(BBC_Micro) https://en.wikipedia.org/wiki/Tube_(BBC_Micro)
- NL807 5y agoLooks like a fun project. I should get back in to FPGA tinkering. Last time I played with one was about 20 years ago. I wonder if the development environment has improved since then?
- jacquesm 5y agoYes and no. Much heavier footprint, mostly the same proprietary bs, somewhat faster and much better debugging/simulation tools. Languages have improved somewhat, and as long as you stay within an eco-system and use the vendor supplied tools and software you should be mostly ok, stray outside of that (for instance: open source toolchains for cutting edge FPGAs) and you'll be in for a world of trouble. The fabrics (got a) lot larger and there are some more and interesting building blocks to play with. Higher switching speeds. Someone who is more active in this field may have a more accurate and broader view than I do. https://symbiflow.github.io/ https://symbiflow.github.io/ Is one of the most recent and - for me - significant developments. Note that for companies that use FPGAs none of the above is considered a hurdle, though their engineers may have a different opinion and that the hobbyist/hacker market for FPGAs is so insignificant compared to the professional one that the vendors do not care about catering to it.
- kragen 5y agoI think there are a lot of major developments in the last 20 years, although I'm not active in the field. Symbiflow is largely a distribution of yosys, a bunch of other IceStorm projects, and nextpnr (is that part of IceStorm?), in the same sense that Debian is a distribution of Linux. Another one, but I think limited to Lattice FPGAs, is https://github.com/FPGAwars/apio https://github.com/FPGAwars/apio. I think the biggest development, though, is that there's enormously more off-the-shelf Verilog and VHDL, not just on OpenCores like 20 years ago, but also on GitLab, GitHub, and so on. Easy examples are CPUs like James Beckman's J1A, the VexRiscv design used in Bunnie's Precursor: https://github.com/SpinalHDL/VexRiscv https://github.com/SpinalHDL/VexRiscv (as little as 504 Artix-7 LUTs and 505 flip-flops), and Google's OpenTitan. But from my POV the more interesting reason for using an FPGA is for things that aren't CPUs. For example, the SUMP logic analyzer and its progeny OLS https://sigrok.org/wiki/Openbench_Logic_Sniffer https://sigrok.org/wiki/Openbench_Logic_Sniffer (32 channels at 200MHz), although I think both of these require the proprietary vendor tools to synthesize. I'm gonna go out on a limb here and guess that reliably buffering up data at 6.4 gigabits per second is not a thing that any CPU can do, even one that isn't a softcore; CPUs that run at speeds high enough to potentially do it invariably depend on cache hierarchies that monkeywrench your timing predictability. As I said, though, I'm not active in the field, so all I know is hearsay.
- marktangotango 5y agoI'd also add as a bystander, that fpga providing onboard hardware for things like DDR3/4 and PCIe seem like significant development. Really tremendous performance is available in these devices.
- tyingq 5y agoSimilar for the Z80... There's an FPGA soft core called nextz80 that's supposed to do 4x more per clock cycle than a normal z80. "Works at up to 40MHZ on Spartan XC3S700AN speed grade -4) - performances similar or better than a real Z80 running at 160Mhz." https://opencores.org/projects/nextz80 https://opencores.org/projects/nextz80
- thrtythreeforty 5y agoWouldn't be hard to beat the z80, it's microcoded and can only retire one instruction every 4 cycles
- jazzyjackson 5y agoAt the Vintage Computer Fest last week Bill Mensch mentioned to the audience that no one ever hears about the 65C02 and 65C816’s use in defibrillators and pacemakers - life critical applications - unless he tells them! Does anyone know of good write ups or explanations of what makes the 6502 so reliable and what competition it had in being chosen for medical applications?
- yitchelle 5y agoI don't have any documentation but I would imagine that as these chips have been in existence for so long, its behaviour is extremely well understood, including most, if not all, of its weak points. The work around for these weak points should also be well known.
- flohofwoe 5y agoThe nice thing about the 6502 is that it is completely reverse engineered down to the transistor level, so it's possible to explore what exactly is going on in the chip for each clock cycle even when the original design documents had been lost: http://visual6502.org/JSSim/index.html http://visual6502.org/JSSim/index.html (and shameless plug, my own 'remix' with better performance and more features: https://floooh.github.io/visual6502remix/ https://floooh.github.io/visual6502remix/)
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- flohofwoe 5y agoThat idea to treat some memory regions (e.g. memory mapped IO areas) as "external memory" which cause the CPU to run at the system clock speed (instead of the much faster "internal clock") sounds like it could also work well for (software) emulators. However for "highly integrated" home computers like the Atari 8-bitters and C64 I guess this wouldn't be of much use, because most games and demos depend on proper CPU timing, even when not accessing memory mapped IO regions (for instance in wait-loops to get to the right raster position before reprogramming the video output).
- djmips 5y agoThey are already caching / stimulating system memory so why not go the next step and simulate the other devices attached to the bus. ;)
- cdcarter 5y agoThere's a lot of discussion of wait stating and slow-clocking of 6502 and accessories over at 6502.org. In particular, many 65xx series accessories still need a common/regular clock signal to keep their internal timers going, even if the CPU is running faster/slower than normal for a specific access. This ends up becoming a very fun design problem when you do it with integrated circuits!
- 300bps 5y agoC64 I guess this wouldn't be of much use Correct, and even more - the Commodore 64 used a 6510 processor, not a 6502 processor. They're similar but there are significant differences. https://en.wikipedia.org/wiki/MOS_Technology_6510 https://en.wikipedia.org/wiki/MOS_Technology_6510 Beyond that, a 6510 isn't the only thing you really need to emulate a Commodore 64. You also need a SID Chip (MOS 6581) for sound and a MOS VIC-II for display and a number of other things.
- vidarh 5y agoThe only difference that matters is the IO pins mapped to address $01. Given this is an FPGA based project it likely would be pretty trivial to make it work in a C64 as well.
- MarkusWandel 5y agoThis is somehow super retro cool. I remember the 8032 being the most serious computer I'd seen to date. Wordpro 4+ and something called "The Manager" in use at my high school, plus the rebadged daisywheel printer Commodore had at the time (CBM 6400?) just had "serious computer" written all over them, right before the IBM PC steamrollered all of that into oblivion. 100MHz. The software you could run! Add a megabyte or so of full speed, pageable RAM expansion. Every computer language right up to C++ (if it works on the 8-bit Arduino it could be shoehorned into a fast 6502 - limited stack? Who cares, just do the big stack in software. Special zero page? Just use it as glorified CPU registers). What's the point really? But awesome all the same.
- jandrese 5y agoA megabyte of ram on a machine with only a 16 bit address space gets a bit silly. Do you really want to manage 16 memory pages? These aren't multitasking machines, what are you going to do with that ocean of memory you can't access without faulting?
- detaro 5y ago> These aren't multitasking machines Why wouldn't a faster machine with more RAM be a multitasking machine? (Obviously without extras you are limited regarding security etc, but plenty early multitasking machines didn't have that)
- flenserboy 5y agoIndeed. Consider that this was done even for some of the more primitive machines of the day — https://en.wikipedia.org/wiki/MP/M https://en.wikipedia.org/wiki/MP/M
- jandrese 5y agoWithout a memory mapper or scheduler it's hard to write a multitasking OS.
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- jhgb 5y agoFinally, C64 GEOS running at acceptable speeds? That might be an interesting thing to try...
- coldacid 5y agoNope. This thing doesn't talk 6510 nor supports the ROM banking used by the C64.
- jhgb 5y agoQuoting from the page itself: "It may be possible and worthwhile to also support some slightly later machines: The Acorn BBC Micro, Atari 400 and 800, and maybe the Commodore C64 come to mind." So support is definitely under consideration.
- vidarh 5y agoIt'll take a more extensive modification than I thought, though, because it does a RAM mirroring thing that is necessary for performance but that kills compatibility with at least the C64. If you disable the RAM mirroring, all you need to make it compatible is to map the 6 IO pins to address $1. That "solves" the bank switching, but at the cost of killing performance totally as the chip will be starved for memory access most of the time. Judging from his pictures, he's using a version of the Spartan 6 (XC6SLX9) that has 72KB on-chip RAM, though, so unless he's using any of the RAM for anything else he could still mirror both the 64KB RAM + the KERNAL and BASIC ROMs. But he'd also need to keep track of various VICII registers to know which areas to designate as a "IO areas" to pass through writes for, given the VICII can address memory "everywhere" for sprites, fonts and bitmap data depending on what you write to different registers. Since that can at any time it'd involve a lot of "fun" logic to flush data from the on-chip cache to the C64 memory if a register changes.
- vidarh 5y ago6510 compatibility only requires adding 6 IO lines mapped to address $1 though (otherwise the 6510 is 6502 compatible enough), so given it's an FPGA based project it wouldn't necessarily be a big ask, and from the webpage it sounds like they're open to suggestions.
- xioxox 5y agoI was wondering how quick an emulated 6502 could go. This project claims 10GHz+ using JIT emulation: https://github.com/scarybeasts/beebjit https://github.com/scarybeasts/beebjit
- marcodiego 5y agoThat's cheating. JIT is more recompilation than emulation.
- ncmncm 5y agoCheating is the name of the game.
- coldacid 5y agoYeah, but that's not a hard/firmware replacement. Besides, JITs are cheating :D
- xgkickt 5y agoWhen diamond semiconductors get to sufficient transistor counts, I wish for an 80GHz 6502 demonstration device.
- ncmncm 5y agoThere are supposed to be 50GHz gallium-nitride FPGAs. Might not be big enough to host a 6502 and all its RAM, though. I gather they are mostly used in military SDRs.
- marktangotango 5y agoWhere would one learn more about these exotic parts?
- ncmncm 5y agoProbably by working at a military contractor. The parts are probably still way too expensive for any other use, and probably too specialized for signal processing.
- kabdib 5y agoLeonard Tramiel once told me that the "world's record" for a production 6502 was around 25Mhz before the smoke came out. This was in a lab at Commodore, and beer was probably involved (and may have been used to cool the chip).
- _abox 5y agoReminds me of when I worked at a computer shop in the Pentium 1 days.. Motherboards had these complex blocks of jumpers in those days to configure the speeds, there was no autodetecting the CPU. One day I was working at a different branch filling in for someone on sick leave, and I spent an hour trying to get a PC I just built to boot reliably. Every time it crashed after an minute or so. I didn't get it, everything seemed fine. Eventually it turned out the "cheat sheet" they had of the jumpers was upside down over there. Someone had copy/pasted the pictures so it was matching the orientation of how they usually had the PC on the desk, rather than upside-down as I was used to. But the text was the right way up. So the total thing looked the same as in our branch except it wasn't. It was a square block so I hadn't noticed the orientation was different. Turned out I had the 100Mhz pentium configured for 180Mhz. Oops. That wasn't even an officially supported speed of the motherboard but the BIOS messages indicated this (which I only noticed afterwards) As we didn't want to sell this CPU after the torture I had put it through we decided to use it for a display box instead, and we tried to keep it running as long as possible by using compressed air cans upside down to blow dry ice :D It actually ran reliably until the can ran out. Only later I found out that liquid nitrogen extremeclocking was actually a thing :D
- zwieback 5y agoGreat story. I remember those days well, I also remember finding every last byte of UMB, elaborate autoexec.bat files and figuring out IRQ assignments to get max functionality. Kids these days don't know how good they got it.
- necovek 5y agoYou mean how bad they got it? :D I loved modifying CONFIG.SYS with a hex editor to translate MS-DOS 6.2 (?) boot menu.
- plandis 5y agoYou’re pretty close to the 2A03 used in the NES, wonder if you could get that to work? I doubt the pin out is the same as the 6502 though.
- rzzzt 5y agoDecimal mode is nerfed on that version, plus some other changes. But like with the 6510 mentioned above, the design could be adapted to match.
- phkahler 5y agoOne problem with the Atari 400/800 computers is that they have the ability to use any part of the 64k address space as frame buffer. You might ran zero page on the FPGA and any ROM from a cartridge to get some performance boost though.
- GekkePrutser 5y agoWow... Really really well done. I love people that throw themselves at a problem that has no real use but just want to master technology. Kudos!! The board design is a masterpiece too. Really clean.
- e-bastler 5y agoThank you so much! And kudos for fully understanding the intent and spirit of the project. :)
- js2 5y agoThis got me thinking about the CPU accelerators that were available for the Apple ][ line, including the GS's 658C16. I googled and little did I know that there's an enthusiast community still developing for it, that's gotten the GS is up 18 Mhz: https://wiki.reactivemicro.com/TransWarp_GS https://wiki.reactivemicro.com/TransWarp_GS
- OnlyMortal 5y agoWay back when, in the early 90s, I ported a unix 6502 C64 emulator to Macintosh (Classic of course). I used it to play ripped Rob Hubbard tunes when the printer ran out of paper. It surprised the end users who’d been ignoring the original SysBeep(1) sounds the application previously used.
- AlexCoventry 5y agoImagine a beowulf cluster of these.
- rzzzt 5y agoImagine a GPU based on 512 of these, with each unit responsible for rasterizing a 128×128 pixel subsection of a 4K frame.
- zsmi 5y agoI don't think that would make a very good GPU as it wouldn't fit the data model well [1] as the instructions and data need to share the same bus which would mess up streaming. Your suggestion is closer to a grid computer but even then I don't think an unmodified 6502 would be a great choice because the memory model (or lack thereof) would really restrict performance. [1] https://booksite.elsevier.com/9780124077263/downloads/advance_contents_and_appendices/appendix_C.pdf https://booksite.elsevier.com/9780124077263/downloads/advanc...
- rzzzt 5y agoSurely the beowulf cluster was a better idea :) Intel did entertain a similar thought for a while, as far as I can understand: https://semiaccurate.com/2012/08/28/intel-details-knights-corner-architecture-at-long-last/ https://semiaccurate.com/2012/08/28/intel-details-knights-co...
- zsmi 5y agoI get that it was mostly a joke. :) The LAN controller used to make the Beowulf cluster would probably have more compute (and memory) than the 6502 itself. The Intel cores in the linked article have a distinct L1 data and instruction caches inside them, and associated L2 caches, which makes a big difference in comparison to the 6502.
- marktangotango 5y agoDreamcast hardware did this sort of "tiled" rendering if I recall correctly. https://www.copetti.org/writings/consoles/dreamcast/#architecture https://www.copetti.org/writings/consoles/dreamcast/#archite...
- amelius 5y agoOne day we'll have these kinds of projects for the M1.
- stragies 5y agoThe ghosts of their armies of lawyers will drive you to insanity if you dare try
- ryanianian 5y ago> The idea of implementing a CPU core inside an FPGA is not new, of course. Indeed. I took a computer engineering class in undergrad. The capstone project was implementing from scratch a multi-pipeline RISC CPU (including the ALU and a very basic L1 cache) in Verilog that we flashed to FPGAs that we then programmed to play checkers using hand-compiled C. The FPGA was easier to flash and debug than the Spartan-6 mentioned in TFA but was significantly more expensive as well. It was a brutal class, but it totally demystified computers and the whole industry in a way that made me feel like I really could understand the "whole" stack. Nothing scares me any more, and I no longer fear "magic" in software or hardware.
- erosenbe0 5y agoAwesome Base to start with! Lot of things in the next step though: PCIE, JTAG, differential signaling protocols, debuggers/monitors, UEFI firmware, cache coherency, TPM type modules, linkers, loaders, vector instruction sets, sound codecs, DACs, GPUs, multi channel SDRAM, MMUs, display protocols, device trees. Plus latency, throughout, and thermal management in any of the above in a real system.
- adamgordonbell 5y agoWow, that sounds like an amazing experience. Challenging though I bet.
- mayli 5y agofull stack engineer vs "whole" stack engineer.
- tomxor 5y agoThere's also adjacent stacks... like being able to build your own computer out of crabs and rocks if you get stranded on a desert island. So that you can get them to write SOS in the sand and play pong while you wait.
- ultimape 5y agoUnconventional computing platforms FTW. https://phys.org/news/2012-04-scientists-crab-powered.html https://phys.org/news/2012-04-scientists-crab-powered.html
- JoachimS 5y agoWay back in 2003 or so, we at my old company InformAsic designed a single chip transparent VPN solution for serial communication (RS-232, RS-422). The control and protocol handling part of the was a modified 6502 core with a sort of MMU and single cycle zero page registers. The whole thing was clocked at 33 MHz, probably making it the fastest 6502 in production at that time. Not that we sold that many of the devices... As an old c64 scener, I really enjoyed being able to code the application SW using my favorite ASM tools. Though most of the code we actually compiled from C using cc65 and then hand tuned to fit the mem constraints. Today a simple Cortex M0+ MCU (with internal AES core) would be able to do what we did, and probably be smaller and require less power.
- klelatti 5y agoOut of curiosity, how does an M0+ + MCU manage to be smaller and more power efficient than something as simple as a 6502?
- compiler-guy 5y agoThe 6502 isn’t manufactured with modern processes and technology. It’s still stuck in the eighties for that sort of thing. So basically everything even a few years newer will be smaller and more power efficient.
- klelatti 5y agoOf course an M0 on a modern process node would be much smaller but I’d interpreted (probably wrongly) the OP as going further and saying that the M0 would be smaller on a comparable node. With 12k or so gates on an M0 that doesn’t seem possible although maybe modern power management would make it more power efficient.
- JoachimS 5y agoNo, that is not at all what I meant. But I agree that I could have been more clear.
- amatecha 5y agoIf the author reads this: can you add HTTPS support for your site? :)
- amatecha 5y agoI wonder if this would be possible to run on the Xilinx Kintex-7 FPGA employed in the currently-in-dev SoM board for MNT Reform laptop[0]? I know very little about FPGAs so I don't know if it's easily applicable to other boards or what. I mean, I'm not saying it would be _practical_, but it would be pretty cool! haha :) [0] https://www.crowdsupply.com/mnt/reform/updates/post-campaign-orders https://www.crowdsupply.com/mnt/reform/updates/post-campaign...
- Teknoman117 5y agoIt should be. Looks like bog-standard verilog to me. It just implements the standard 6502 bus rather than something like AXI or wishbone. (link pulled from the references section of the post) https://github.com/hoglet67/CoPro6502/tree/master/src/Arlet https://github.com/hoglet67/CoPro6502/tree/master/src/Arlet
- vidarh 5y agoThe Kintex-7's are much bigger than the Spartan 6's. Getting a 6502 core into them wouldn't be the issue. The special thing about this board, though is that it's designed to be pin compatible with a real 6502 CPU, so you can plug it straight into a real 1970's/1980's home computer that used a 6502. If that's not what you want to do you'd need other glue logic to interface the CPU core with whatever you want to interface it with.
- ChuckMcM 5y agoThis is pretty awesome, and while it "caches" all of memory, it is conceivable you could just run memory cycles the old fashioned way. And while that doesn't give you a speed bump it does give you the worlds most amazing in-circuit-emulator pod for 6502 designs.
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- ddingus 5y agoI have a 16Mhz Apple 8 bit computer. What struck me is how lean early tools and applications really are. Many are just usable at 1 Mhz. At 16, things are generally luxurious. Doing graphics, or writing, even running programs in BASIC all make sense and perform. 100Mhz is crazy! Frankly, one could add to the software and take advantage of the fast electronic storage available today and get real things done. I wonder just what people will wnd up doing on a BBC Micro, or Apple 8 bit machine fitted with one of these. I want one! Fun project.
- cmrdporcupine 5y agoIn reality in a machine like the C64, etc. it wouldn't really run at 100mhz, because in that case the bus speed is driven by the VICII chip and the bus access is stolen by it to do its work, and this is all tied to NTSC/PAL speed. So in the design on this FPGA impl it could theoretically internally do a burst of 100mhz-esque work it would only be while the VIC-II (or equivalent in other machines) has given time over to it. The original article touches on this, the difficulty interfacing an Atari 8 bit, C64, etc.
- ddingus 5y agoYes, and that's precisely why the Apple 2 is still on my hobby / workbench. It's simple to interface with, and with a faster clock, remains useful. And the Apple has slow RAM and fast RAM in a similar way. Really, to get the machine to run at 16Mhz, it's necessary to copy code into the fast RAM on board the card, leaving system RAM unused. The Color Computer, Apple 2 and some others were made in a simpler way that did not interrupt the CPU for refresh and or video access cycles. That makes projects like this easier.
- einr 5y agoThis was already an issue on the Commodore 128, which had a 2 MHz "fast" mode but you had to manually engage it, and doing so would turn off the VIC-II. Good for doing large calculations or working in 80 column text mode, but useless for games etc.
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- corysama 5y agoIf that's not enough, you could check out "Clocking a 6502 simulator to 15GHz" https://news.ycombinator.com/item?id=22859706 https://news.ycombinator.com/item?id=22859706
- 6510 5y agoI often ponder all the work put in to make electronics execute series of instructions one by one but where it is undesirable we often lack abstraction for parallel computing. The funny part is how parallel is so "easy" in electronics. My gut says there has to be some simple approach we've all overlooked.
- analognoise 5y agoVHDL and Verilog on FPGAs/ASIC is parallel - we don't think serially at all!
- userbinator 5y agoThis is not far in concept from modern CPUs where only the core and cache run at full speed, although it might be the first 6502 implemented this way. It reminds me of the upgrade processors for 386 and 486 PCs that had a Pentium and cache in a socket-compatible format.
- TacticalCoder 5y ago> It reminds me of the upgrade processors for 386 and 486 PCs that had a Pentium and cache in a socket-compatible format. "Pentium overdrive": https://en.wikipedia.org/wiki/Pentium_OverDrive https://en.wikipedia.org/wiki/Pentium_OverDrive
- userbinator 5y ago...and here's one in a 386 motherboard, using a 386-to-486 adapter: https://dependency-injection.com/pentium-on-a-386-motherboard/ https://dependency-injection.com/pentium-on-a-386-motherboar...
- sharmin123 5y agoFacebook Safety Tips: Take Steps Now and Avoid Hacking: https://www.hackerslist.co/facebook-safety-tips-take-steps-now-and-avoid-hacking/ https://www.hackerslist.co/facebook-safety-tips-take-steps-n...
- andrewstuart 5y agoOff topic but the eZ80 supported up to 50Mhz https://en.wikipedia.org/wiki/Zilog_eZ80 https://en.wikipedia.org/wiki/Zilog_eZ80 Datasheet: https://www.mouser.com/datasheet/2/240/ps0066-2584677.pdf https://www.mouser.com/datasheet/2/240/ps0066-2584677.pdf You can buy them still: https://www.mouser.com/Semiconductors/Embedded-Processors-Controllers/Microprocessors-MPU/_/N-6hpeh?Keyword=z80&FS=True https://www.mouser.com/Semiconductors/Embedded-Processors-Co...
- ngcc_hk 5y agoOne thing is whether this can support single step. Strange but that is what we try when hacking the 6502 and some chips are specially designed to allow single stepping.
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- MicroCoreLabs 5y agoThe MCL65+ is also a drop-in replacement for the 6502 which uses an 800Mhz microcontroller to emulate the CPU, so it can run in cycle accurate and accelerated modes. https://microcorelabs.wordpress.com https://microcorelabs.wordpress.com
- MicroCoreLabs 5y agoPS: Same code also ported to the MCL64 which fits in the 6510 socket of a Commodore 64.