10 ms·
An Open-Source FPGA-Optimized Out-of-Order RISC-V Soft Processor (2019) [pdf]
- Symmetry 6y agoTo push this up from the comments, if you're interested in why this is important or what the authors are trying to do the PDF where they describe their approach and architecture is really interesting. http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashimo-FPT'19.pdf http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashim...
- jeff-davis 6y agoIf I understand this correctly: Typically, I think of an FPGA as something used to accelerate specialized operations. But sometimes, in the middle of one of these specialized operations, you might want to do something more general, like run a network stack, without returning to the CPU. A soft processor like this allows you to run an ordinary network stack (with ordinary code) inside the FPGA. Is that right? I thought one of the things people used FPGAs for was accelerating network stacks, so I don't quite know why you'd want to use a soft processor for that. But it does make sense that you'd want to be able to run ordinary code in an FPGA (as part of a larger FPGA operation that is not ordinary code). EDIT: Also, I don't understand this statement: "for example, one main compute kernel, which is too complex to deploy on dedicated hardware, is run by specialized soft processors". What do the authors mean "too complex to deploy on dedicated hardware"?
- mindentropy 6y agoGenerally softcores are used for command and control for the FPGA. For eg you have a framegrabber and you would like to adjust the shutter speed, fps etc you would create a softcore and run normal firmware to setup the registers based on the users choice. You can think of FPGA as an ASIC and the softcore to control this ASIC. The hot data path and heavy processing is done in the FPGA and processing options for the ASIC can be done using the softcore firmware.
- TrueDuality 6y agoIt's definitely common to accelerate specialized operations without the overhead of a general processor, but it's also possible to effectively use them as a much more flexible microprocessor when you need it. If you go looking for a microcontroller for your project, you have to choose among what is available. Maybe this microcontroller has two hardware UART interfaces and 1 SPI interface. If I don't need any UART but instead need a CANBUS interface that microcontroller won't work for me. Sure I can bitbang the protocol on GPIO ports but that uses up a lot of the limited processing power on the microcontroller... Usually that means a more expensive microcontroller. There is a threshold that you can cross where a small FPGA is cheaper than a microcontroller that has enough pins and processing power for your application. This does come with an additional upfront design cost of also writing (but more often integrating) the soft cores but sometimes that makes sense. Sometimes peripherals just don't exist at the price point you need. Try and find a microcontroller that has a MMIO controller for under $5 (I probably couldn't do it at under $10 but I haven't gone looking recently), it's rare they're needed but sometimes a design requires one. There has also been a lot of recent interest in doing formal verification of hardware logic. A lot of the microprocessors and even that full CPU in whatever device you're reading this on has a lot of undocumented black boxes and undefined behaviours both of which prevent that verification from being meaningful.
- lizknope 6y agoTo make a custom chip it requires one time mask fees of up to $30 million for a 5nm chip. If your volume is high then you can amortize that cost. If not then you probably go to an FPGA. An FPGA has a high per part cost but no custom mask costs and you can reprogram it in a few hours / days instead of 2 months for a new custom chip to be manufactured. A high end FPGA already has hardened CPU blocks, USB and PCIE interfaces, and lots of other things built in. Then it has a large area of generic reconfigurable logic that you can customize to do whatever you want. This reconfigurable logic will not be as fast as a custom chip but it is still far faster than software and can be used to implement your own CPU (assuming you don't want to use the hardened CPU or got an FPGA without them)
- mng2 6y ago>What do the authors mean "too complex to deploy on dedicated hardware"? It costs time and effort to translate a software function to HDL/FPGA, so it's not always worth doing. For example you could do TCP/IP in hardware, but unless you have particular performance requirements (say HFT) you're probably better off with a soft core and a tested software TCP/IP stack. Also each feature translated to hardware takes up space in the fabric. When you crunch numbers on an FPGA, it's ideal if you can lay out the entire sequence of operations as one big pipeline, so you can keep throughput as high as possible. Sufficiently long or complex sequences may not translate efficiently to FPGA.
- rcxdude 6y agoFPGAs are frequently not connected with a dedicated CPU at all, and even when they are they may be connected over a link with lower bandwidth/higher latency than you would like. In these cases you usually have a bunch of management and logic tasks which are better suited to a CPU (basically anything with a large number of different serial steps and complex control flow will probably synthesize poorly directly to an FPGA: this is probably what the authors described as 'too complex for dedicated hardware'), so you synthesize a CPU in the FPGA fabric which usually has a direct memory map to whatever registers you need in the FPGA design to accomplish your goals. This is common enough basically every FPGA vendor also sells FPGA SOCs which have a hard CPU attached to the fabric, and if you are using one of those then you will generally not synthesize a CPU in the fabric because it'll usually be slower and less power efficient than the hard CPU you have. But that CPU also isn't free and if your CPU compute requirements are not particularly high than the soft CPU might be more efficient for your usecare (or a hard CPU may not be an option in the range you need).
- dang 6y agoOk, we've changed the URL to that from https://github.com/rsd-devel/rsd https://github.com/rsd-devel/rsd, which doesn't give much background.
- CodesInChaos 6y agoIs there a quantification of "high performance"? It will obviously be much lower than the IPC of an actual high performance CPU (modern x86-64), but how big is the difference? And how does it compare to typical mobile processors?
- NieDzejkob 6y agoI believe the closest measurement would be in Table VII on page 8 of the paper: http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashimo-FPT'19.pdf http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashim...
- childintime 6y ago"In comparison to the BOOM, the RSD achieved 2.5-times higher DMIPS and 1.9-times higher DMIPS/MHz", which should be comparable to ARM cores around 4 years ago.
- Veedrac 6y agoNote that BOOM is now on v3[1], which claims to be 3.93 DMIPS/MHz, or about twice RSD. [1] https://people.eecs.berkeley.edu/~krste/papers/SonicBOOM-CARRV2020.pdf https://people.eecs.berkeley.edu/~krste/papers/SonicBOOM-CAR...
- deleted 6y ago[deleted]
- jhallenworld 6y agoRV32IM, 2.04 DMIPS/MHz, 95.3 MHz, 15K LUTs, 8K LUT FFs, 6 BRAMs on Zynq 7020. I'm curious if this will work on Lattice ECP5- I'm not really sure if Synplify supports system verilog to the same degree as the Xilinx tools. ECP5 is interesting because it's a $10 FPGA..
- mhh__ 6y ago
- smrxx 6y agoAll those abbreviations on the block diagram make it very difficult to interpret. A key map in the image would be great, or at least some markdown directly below it.
- xiphias2 6y agoI guess somebody will implement 64 bit GC extensions to run linux on it.
- chrisseaton 6y agoGC extensions? What does 'GC' stand for?
- the_duke 6y agoG is short for MAFD (multiplication, atomics, floats, doubles) and C for compression. See https://en.wikipedia.org/wiki/RISC-V#Design https://en.wikipedia.org/wiki/RISC-V#Design .
- chrisseaton 6y agoAh sorry I get it - ISA extensions - I thought it was compiler extensions.
- FullyFunctional 6y agoAhem, you need to full supervisor support as well with virtual memory (page table walkers, TLBs etc). And atomics. And floating point (etc). This is all non-trivial and would make the design ~ twice as big and likely impact the cycle times in a rather sad way. But possible of course. Anecdata: Full RocketChip (RV64GC) built for ECP5 85F comes in at 54k LUTs (out of 84k) and clocked at 14.8 MHz. However, the cycle time is related to the FPU which assumes retiming which yosys can't do. Without the FPU it's a more reasonable 50-60 MHz.
- monocasa 6y agoI don't think it has an MMU (didn't see a TLB or table walker in the source), so a lot more work is needed than just the extra instructions.
- choletentent 6y agoI am glad they are using System Verilog. It is hard for me to understand why SiFive chose Chisel as RTL language. I think that quietly slows down the RISC-V adoption. I honestly tried to understand the advantages of Chisel, but I can not see any. There is an answer on Stack Overflow regarding Chisel benefits, it is just embarrassing [1]. [1] https://stackoverflow.com/questions/53007782/what-benefits-does-chisel-offer-over-classic-hardware-description-languages https://stackoverflow.com/questions/53007782/what-benefits-d...
- unionpivo 6y agoPlease note I am software dev, not a hardware guy, and I just got my first FPGA during holidays, and am just beginning to play with it. > There is an answer on Stack Overflow regarding Chisel benefits, it is just embarrassing [1]. I don't understand what is embarrassing about the answer ? As a software guy above answer make sense. Some problems you want to use C (or similar) for and some problems you want to use scripting language for, and then again sometimes the right tool is erlang, rust or go-lang ... But like I said, that's my software guy perspective, so I am wondering what I missed?
- alain94040 6y agoI just read the answer as well. It's not "embarrassing", but it basically doesn't answer the question. Instead, it argues that the question is equivalent to asking what's the point of Python vs. C. So in the end, the answer doesn't provide any specific answer regarding SystemVerilog and Chisel. All I found is one mention of negotiating parameters, which Verilog doesn't do. I would have loved to hear a lot more about examples of what Chisel makes more convenient than SystemVerilog.
- nickik 6y agoThere are tons of people using System Verilog for RISC-V. The majority of work done is with System Verilog and not Chisel. Having lots of cores in both Chisel, System Verilog and many other languages (VHDL,BlueSpec and so on) is a huge benfit for RISC-V SiFive values programmability above everything and for that Chisel is pretty clearly an advantage.
- mhh__ 6y agoWell done to the authors for making a surprisingly readable core for once.
- londons_explore 6y agoThe gif of the Konata pipeline visualizer seems to show pretty much one instruction per cycle most of the time... Many parts of the trace show as low as 0.2 instructions/cycle.. Wouldn't we expect much higher numbers (more parallelism) considering the number of frontend/backend pipelines?
- _chris_ 6y agoSpoiler-alert, even your x86 desktop cores struggle to hit more than 1 IPC on most workloads. That's just the reality of cache misses, instruction dependencies, branch prediction, and more.
- dpoochieni 6y agoIf the FPGA is a closed-design are we really that better off?
- rwmj 6y agoThere are fully reverse-engineered FPGAs and open source toolchains to drive them. The real question is: Is there anything hidden in the silicon? That's something you can only solve by owning your own fab - the US military approach.
- eeZah7Ux 6y agoGood luck hiding an effective backdoor in an FPGA. The attacker (the FPGA fab) has no idea of how it's going to be programmed.
- rwmj 6y agoThe usual thing the military worries about is a "kill switch" (a very unlikely sequence of bits) which disables the hardware completely. The idea is that at the beginning of a war, the kill signal is broadcast by the enemy by every means possible which brings all your electronics to a halt. This can be hidden in an FPGA - for example attached to the input pins or SERDES - without needing to know anything about the application. (Article: https://spectrum.ieee.org/semiconductors/design/the-hunt-for-the-kill-switch https://spectrum.ieee.org/semiconductors/design/the-hunt-for...)
- eeZah7Ux 6y agoTriggering a malfunction is incredibly easy compared to a proper backdoor. A kill signal could also be injected through side channels e.g. a power line, and the kill mechanism could be implemented in many other semiconductors than an FPGA.
- fest 6y agoThe argument here usually is: with a fixed silicon chip, vendor can hide the backdoor in various locations and be it triggered by various events (e.g. a particular sequence of incoming ICMP packets would overwrite the first byte of response with content of some register). With FPGA, the vendor can't really know where a particular register is located, or where incoming packets are processed, as it is highly dependent on the synthesised CPU design and can even be non-deterministic. This does not mean that there is no way vendor can backdoor the chip you are getting, but it does narrow the possibilities significantly.
- ecesena 6y agoIs anyone working on low power open risc-v implementations? (Ideally including manufacturing, i.e. a physical device that I could buy/build on top of)
- blacksmith_tb 6y agoSeeed has some RISC-V Arduino-alikes [1], but my memory is that they have teased a more substantial, linux-capable board here in Q1. 1: https://www.seeedstudio.com/SeeedStudio-GD32-RISC-V-Dev-Board-p-4302.html https://www.seeedstudio.com/SeeedStudio-GD32-RISC-V-Dev-Boar...
- blacksmith_tb 6y agoOops, my bad, it's Sipeed! https://www.cnx-software.com/2020/11/09/xuantie-c906-based-allwinner-risc-v-processor-to-power-12-linux-sbcs/ https://www.cnx-software.com/2020/11/09/xuantie-c906-based-a...
- nereye 6y agoOne of the two ULP (Ultra Low Power) co-processors on ESP32-S2 chips is based on RISC-V. Boards using ESP32-S2 are available for relatively little, e.g. see https://www.mouser.com/ProductDetail/Espressif-Systems/ESP32-S2-Saola-1R/?qs=GBLSl2AkirsMIxW%2FKjKKRw%3D%3D https://www.mouser.com/ProductDetail/Espressif-Systems/ESP32.... It's admittedly a niche use-case but it's an option for playing with RISC-V hardware...
- oblio 6y agoFor people in the industry: how likely are we to get RISC-V servers/VMs/laptops/desktops in the next 5-10 years? You know, go on a PC Part Picker and assemble a RISC-V desktop, for example.
- jagger27 6y agoCan you go on PC Part Picker and build an Arm desktop yet?
- oblio 6y agoI haven't tried, I assume not. But aren't the hardware fashions changing rapidly now? Compared to 2005-2020, with x86 everywhere I mentioned.
- moyix 6y agoSure, order a Raspberry Pi 4 and an external USB SSD ;)
- AceJohnny2 6y agoso fun fact: I was recently curious how the RasPi4 compared to my 15-year old Dell Precision M65 (Intel Core Duo T2400). I ran the sysbench CPU test on each, and the M65 trounced the RasPi4, being over 3x as fast in single-core (and about 1.5x as fast in multicore, which makes sense with the T2400 being 2-core to the RasPi's 4-core). So the RasPi4 (a cheap-class SoC) remains slower than a performance-class PC from 14 years prior. Moore's law certainly helped in peformance-per-watt and performance-per-dollar, but if pure perfomance is what you want... I don't think there's anything available to consumers outside of Apple's offerings.
- anfilt 6y agoPart of ARMs licensing generally prevents socketed CPU chips.
- mancaus 6y agoI'm not in the industry - just dabbling, but SiFive have a mini-ITX with all the expected interfaces[1] available for pre-order. The Mouser link lists March for the initial deliveries. The Getting Started Guide indicates it comes with a micro-SD with a bootable Linux image, but mostly goes on to describe console access. That said, it does recommend a GPU, but it's unclear whether it can boot to a graphical desktop out of the box. [1] https://www.sifive.com/boards/hifive-unmatched https://www.sifive.com/boards/hifive-unmatched
- ruslan 6y agoI know Yosys has a limited support for System Verilog, but any success synthesizing this using FOSS toolchain ? What features are missing if not successful ?