14 ms·
5nm vs. 3nm
- baybal2 7y ago> There are fewer foundries to choose from at the most advanced nodes To the effect, only two. It is surprising just how fast it has turned into a duopoly. Samsung and TSMC are now the Airbus and Boeing of semiconductor industry
- Etheryte 7y ago> The cost to design a 3nm device ranges from $500 million to $1.5 billion, according to IBS. Process development costs ranges from $4 billion to $5 billion, while a fab runs $15 billion to $20 billion, according to IBS. At these scales, very few players can afford to play, even if a breakthrough could net you a very comfortable position for many years.
- teraflop 7y agoOut of curiosity, do you know what factors are mainly driving the costs so high? Thinking about it naively, I can guess at a few possibilities: - it's highly labor-intensive - it requires highly specialized skills that command incredibly high prices on the labor market - it requires lots of prototyping iterations that require expensive materials - the prototypes are produced on machinery with high opportunity costs - IP licensing costs I'm wondering if one of these in particular is the dominant cause, or if it's all of them in conjunction, or if there are other major factors I'm not thinking of.
- ekianjo 7y agothe cost of highly specialized machinery is certainly a big driver. Plus that machinery is basically thrown away every time you go to a thinner process. Also, figuring out how to maximize yields to an acceptable level must be a lot of experimentation.
- pkaye 7y agoI used to work on R&D on development of those expensive FAB machines. There was lots of expensive materials to meet extreme requirements. The process chambers were hot with corrosive gases. For example you couldn't use cheap o-rings. Instead of $30 standard o-rings, we would need $3000 chemical resistant o-rings that don't disintegrate with time. You had to trace down minute sources of contamination. And there was lots of iterations of prototyping to get things just right.
- klyrs 7y agoLithography is actually a huge challenge, and is becoming extremely complex https://semiengineering.com/7nm-fab-challenges/ https://semiengineering.com/7nm-fab-challenges/
- brennanpeterson 7y agoA process cost is basically the 2 years of Fab time. And a Fab is expensive due to the capital equipment (your opportunity cost). A 10B Fab Costa about 2B per year, thus process development is 4B. I think those design costs are nonsensical. There are major projects done by groups of 100 or fewer engineers. A really unique design can cost that much, but a licensed design built.on standard cells is less. That is how rocketchip, RiscV, and others get by. As an approximation, every M$ is 2 engineer years. A 100M$ design is...200 engineer years. With an ARM license and other IP, that is likely manageable. There is a large infrastructure of design tools that keep design costs constrained per design. Fab costs are not so easily limited....
- JudgeWapner 7y agoI just quit a gig at a semiconductor supplier that makes EUV light. Keep in mind this is just one major component in the chain: - EUV comes from a plasma of metal created in a vacuum chamber. - the plasma is created by concentrating a beam of light on a tiny pellet of molten metal - that beam of light is a 25kw laser, which is borderline weapons-grade. To the point that countries hesitate to even allow it to be imported. - the laser must be pulsed precisely to vaporize the metal as its flying through the chamber - residue from the metal vapor quickly builds up and deteriorates the process getting this stuff to work requires armies of engineers and scientists. the machines themselves are the size of a tour bus.
- p1esk 7y agoIntel is still ahead of them, right? Last I’ve heard they are moving pretty aggressively on their “7nm”, which is supposed to be at least as good as TSMC’s “5nm”. Compare min metal pitch for Intel’s “10nm” (36nm) and TSMC’s “7nm” (40nm) [1] [1] https://en.wikichip.org/wiki/10_nm_lithography_process https://en.wikichip.org/wiki/10_nm_lithography_process
- TomVDB 7y agoWhat does it mean to be ahead in 7nm when you are years behind in getting your 10nm process into acceptable yielding mass production?
- p1esk 7y agoI don’t see why they can’t be both behind on “10nm” and ahead on “7nm”.
- paulddraper 7y agoYes, they are substantially different processes.
- benj111 7y agoTrue, but they seem to have been ahead on 10nm until they weren't, which calls into question claims about 7nm. Then there's the question of why they aren't skipping 10nm if 7nm is so ahead. And theres the question of why they can't 'scale up' their 7nm to do 10nm.
- earenndil 7y agoPresumably 10nm is cheaper to produce, so they can use that to make lower-end processors.
- rusticpenn 7y agoThere are two technologies used in etching, UV and EUV. UV was designed for nodes upto 40 nm (approx). EUV can be used with accuracy of 13nm. EUV has been under development for more than a decade in several firms, so companies used several trickes to make use of UV for lower sizes. 10nm is the extreme end of it (I guess). For EUV this is standard range. It should work without any issues until 5nm and then special tricks would be used to make the pitch smaller. So manufacturing 10n, with UV is much harder than manufacturing 7nm with EUV (although it is more expensive).
- bhouston 7y ago> Samsung and TSMC are now the Airbus and Boeing of semiconductor industry Then what is Intel?
- js8 7y agoIf I understand it correctly, 3 nm is less than ten atoms. Cannot this make the technology much less reliable due to quantum effects and interference?
- kragen 7y agoIt's about 30 atoms, depending on the material. Silicon's covalent radius is 111 pm, so it's 27 silicon atoms. But the 3nm process node doesn't mean that all the features are 3nm wide; a lot of things are twice that wide in many processes. Sounds like 3nm is pretty weird, though, so all bets are off. IBM fabricated single-atom transistors that worked with adequate reliability back in the 1990s, IIRC. I don't know how bad the noise problem you allude to really is.
- Certhas 7y agoBut the covalent radius is not the crucial property here, the silicone lattice spacing is, and that's 0.5nm so a 2nm wide element is 4 atoms across.
- Certhas 7y agoCorrection: The lattice spacing gives the size of the fundamental building block of the lattice, which includes several atoms. The nearest neighbour distance in the lattice is 0.235 nm. Wikipedia has a nice picture of the lattice structure: https://en.wikipedia.org/wiki/Diamond_cubic#/media/File:Visualisation_diamond_cubic.svg https://en.wikipedia.org/wiki/Diamond_cubic#/media/File:Visu... Part 3 of the picture is a 3x3x3 block of elementary cells, for silicon this would be 1.63nm along each edge, so for a 2nm element you get a few more atoms in each direction.
- kragen 7y agoThank you both for the correction!
- deepnotderp 7y agoNode names stopped meaning anything a long time ago, it's not really 3nm, that's just the marketing name. Think 11 inch "Footlong" but more extreme. That being said, direct S/D tunneling is expected to become an issue at channel lengths of around 1nm, although anisotropic carrier mass can be used to delay this further.
- kragen 7y agoI didn't realize Samsung was offering a 5nm process to customers; this means that TSMC is not the only 5nm foundry out there, as I thought it would be when GlobalFoundries canceled their 5nm R&D program. And it sounds like competition might keep process shrink alive for at least one more node, down to 3nm, although there's a good chance that either Samsung or TSMC will have to bow out at that point. Since Dennard scaling ended about 15 years ago, these new devices will probably run hotter, adding to the dark-silicon, eh, let's call it a situation. It's a problem from the traditional point of view where you expect to be able to use all your hardware all the time, but maybe it's an opportunity if you see it as a chance to handle burstier computational loads or to pack a greater diversity of specialized cores onto a chip. But of course that increases both design costs and the complexity of programming the device once it's been fabbed. The impending collapse of Moore's Law has thus been delayed for two or three years, or softened anyway, but the appetite for computation due to deep learning continues unabated. Since scaling Jack Kilby's planar process down is becoming increasingly uneconomic, this would be a good time for a non-planar process to emerge — a trillion squares occupies a one-million by one-million area, while a trillion voxels is only ten thousand by ten thousand by ten thousand, a scale a hundred times larger and therefore less demanding on your fabrication processes. You'll probably need some plumbing in there for coolant. I don't know of anybody working on this, surprisingly.
- sbierwagen 7y agoWhat about https://nanoheat.stanford.edu/sites/default/files/publications/B10.pdf https://nanoheat.stanford.edu/sites/default/files/publicatio... ? No commercial projects that I know of, though.
- deepnotderp 7y agoSo it turns out that microfluidics isn't really the best solution since you more or less need cooling channels between the layers and microfluidics is too big for that (without extreme pressure drops) for truly useful 3D integration. Source: I work on 3D chips for deep learning
- beautifulfreak 7y ago
- guardiangod 7y agoI've been following fab news for close to 2 decades already. I am familiar with all the major players in the market, but this article keeps mentioning SMIC. Now I know SMIC since its creation, but afaik it has always been several nodes behind leading edge, and never scored any major contract. Without any large production contract, how does it get enough experience to even get to 7nm? UMC, their partner, pretty much gave up on 7nm already. TSMC has resisted all attempts at espionage. Is it from Samsung?
- microcolonel 7y agoWell, there are lots of possible factors: a) China is turning inward, maybe they're getting some state support, monetary, political, or otherwise; or at least benefiting from a lucky coincidence. b) SMIC has been credibly accused of misappropriating TSMC secrets in the past, and settled. c) I think a number of major Chinese manufacturing companies invest resources and money in them, possibly as some form of insurance policy. d) The Chinese government does procure armaments, maybe SMIC does manufacturing they've been asked not to talk about.
- bcaa7f3a8bbc 7y ago> China is turning inward, maybe they're getting some state support, monetary, political, or otherwise; This seems to be the most likely factor.
- gvb 7y agoYes, it is an explicit strategic policy of the Chinese government as part of "Made in China 2025" with state support (political and monetary). https://en.wikipedia.org/wiki/Made_in_China_2025 https://en.wikipedia.org/wiki/Made_in_China_2025
- bcaa7f3a8bbc 7y agoA more direct motivation is recent U.S. sanctions on Chinese companies, the state support in semiconductor section has been boosted significantly, since decision-makers in China is now seeing the lack of state-of-art semiconductor manufacturing capabilities a critical threat to national security. Plausibly, developing the domestic semiconductor market to reduce foreign reliance is going to be a major goal. As we see, SMIC has already withdrawn from New York Stock Exchange entirely [1], and purchased a 7nm EUV lithography machine from ASML for $120 million [2]! [1] https://www.scmp.com/business/article/3011737/chinas-biggest-chip-maker-smic-withdraw-new-york-stock-exchange-trade-spat https://www.scmp.com/business/article/3011737/chinas-biggest... [2] https://www.anandtech.com/show/13941/smics-14-nm-mass-production-in-1h-2019 https://www.anandtech.com/show/13941/smics-14-nm-mass-produc...
- agumonkey 7y agoHow long until you can get flagship smartphone performance under a Watt ?
- sharpneli 7y agoYou can get flagship from maybe 4 years ago under a watt today. In future you can get current flagship under a watt too. But then the new flagship with it’s 5W consumption will be so much better.
- agumonkey 7y agoOnly asking because under a Watt you get reliable small solar powered SoC
- simongr3dal 7y agoSmall solar powered like with calculators and their roughly 1” sq. solar power strip? That would be amazing but probably not feasible with the kind of display people have come to expect on their smartphone.
- bhouston 7y agoMaybe they can figure out how to embed a solar panel into the display. I guess it would absorb light though so it may be hard to balance with a light emitting display. I wonder if one can be very specific on directionality for both emission (outward direction only) and absorption (inward coming light only.) Logically I would think the emission layer goes on top of the absorption layer. This seems on the face of it possible. I do not know enough about the specifics if it is reasonable to do. I could see it though. Just leave your phone face up on your desk during the day to have it charge.
- agumonkey 7y agoI was just wondering about that. But light emissions would probably cancel solar intake.
- kingosticks 7y agoCan someone explain why the supply voltage for traditional finFETs can't be taken below 0.75V as is quoted in the article? Are they just talking from a mass production yield perspective?
- bertjk 7y agohttps://en.wikipedia.org/wiki/Threshold_voltage https://en.wikipedia.org/wiki/Threshold_voltage
- kingosticks 7y agoI guess I was unclear. I am trying to understand why the threshold voltage can't be reduced below what came across as a hard limit of 0.75V. My guess was that even a finFET can't give you the channel control required to prevent the transistor from approaching a lower threshold voltage. Which means it's half-on when it's supposed to be off, which means you've got a lot more leakage. But surely you can tweak it a bit more: make the fin taller, wrap it around the channel a little bit? And then maybe get a slightly lower threshold voltage? Maybe it's just not worth the hassle and having gate all around is a better return.
- jononor 7y agoThese things are generally already tweaked way into the region of diminishing returns. Easy gains are all taken.
- Robin_Message 7y agohttps://electronics.stackexchange.com/questions/286824/silicon-diode-threshold-voltage-0-7 https://electronics.stackexchange.com/questions/286824/silic...
- kingosticks 7y agoThanks! But I guess my point below still stands, it works just fine, it's just leaky.
- rocqua 7y agoWhy are nodes a linear step of 2nm? It seems to me that going from 7nm to 5nm (a factor 1.4) is a smaller step than going from 5nm to 3nm (a factor 1.6666). Not just a smaller step in engineering effort, but also in effect size.
- wtallis 7y agoIt's not a linear scale, it's just that we're still rounding to integers, so we're going from 7 to 5 instead of 4.9 and then to 3 instead of 3.5. Since we've long since departed from having node names correspond to any physical dimension or even a meaningful composite of critical dimensions, the only thing wrong with sticking to simple integer naming is that we might run out of smaller integers before we run out of ways to improve silicon fabrication.
- rocqua 7y agoAh, so its a factor of sqrt(2) on the length scale, corresponding to a factor 2 of area and (I guess) a factor of 2 improvement in transistors/cm^2. Makes sense, thanks!
- abdullahkhalids 7y agoSuppose I have a million dollars. Could I make a fab [1] that can manufacture a Intel 286 processor (with feature size roughly 1.5 micrometer) or equivalent? If not, what year of semiconductor manufacturing technology could I replicate? Wikipedia provides this rough estimate of feature size - year table: 10 µm – 1971 6 µm – 1974 3 µm – 1977 1.5 µm – 1982 1 µm – 1985 800 nm – 1989 600 nm – 1994 350 nm – 1995 What about only a 100K USD? [1] capital costs only. Not labor.
- avs733 7y agoNo. You couldn't even buy the cleanroom building for $1m
- tfha 7y agoYou may not need a cleanroom at that feature size today
- cma 7y agoAlso yield isn't a big concern in a hobby project.
- abdullahkhalids 7y agoUniversity labs often have cleanrooms that definitely do cost roughly on the order of low millions. And they are built to the standards of 2010s fabrication requirements. Replicating 1980s cleanroom requirements today would be a lot cheaper. Edit: Page 64 of the pdf https://dokumente.unibw.de/pub/bscw.cgi/d9262701/01_History.pdf https://dokumente.unibw.de/pub/bscw.cgi/d9262701/01_History.... suggests in 1980 the total investment cost of a fab was $100million. I would expect that same tech could be replicated a lot cheaper today. A 100x improvement doesn't seem outrageous.
- 0xffff2 7y agoI don't see anything on that slight that indicates whether the numbers are inflation-adjusted or not. $100million in 1980 dollars is ~$300million in 2019 dollars. That's going to eat into your savings quite a bit. I'm no expert, but a 100x savings seems pretty outrageous to me and 300x even more so.
- eloff 7y agoMoore's law is dead, but I don't think the story ends there. Now the incentives exist to explore alternatives to Silicon, which could yield many more years of big process improvements. While Silicon was scaling so rapidly there was little point in investing in alternatives. The free lunch is over, but the stage is set for the next act of the microprocessor revolution.
- msla 7y agoI wonder if architectural diversity will increase even further than it has. It's already increased a bit in the microprocessor world with the rise of GPUs, but that "just" puts supercomputer-style vector processing in SBCs and laptops. It isn't as new of a concept as systolic arrays, for example; those can be fast even on slow hardware if you pick your problem right, just like how GPUs are only speed demons on certain tasks. Well, if we can't beat problems to death with increasing scalar speed, it might give us more incentives to design ever-more-specialized chips which solve specific problems extremely effectively even if they're comically useless for general-purpose computing.
- stcredzero 7y agoWell, if we can't beat problems to death with increasing scalar speed For those not immediately familiar with the terminology: "scalar" is Single Instructions, Single Data. https://en.wikipedia.org/wiki/Flynn%27s_taxonomy https://en.wikipedia.org/wiki/Flynn%27s_taxonomy
- Nuzzerino 7y agoRay Kurzweil has long predicted 3D computing chips would become a paradigm. I'm not talking about GPUs, but actually vertically stacked layers of transistors. https://www.kurzweilai.net/radical-new-vertically-integrated-3d-chip-design-combines-computing-and-data-storage https://www.kurzweilai.net/radical-new-vertically-integrated...
- eloff 7y agoThis has arguably already been appearing on the graphics side with stacked memory, but now Intel is getting serious about this approach: https://www.theverge.com/2019/1/7/18173001/intel-lakefield-foveros-3d-chip-stacking-soc-design-ces-2019 https://www.theverge.com/2019/1/7/18173001/intel-lakefield-f... A big problem is heat. But stacked designs produce less heat overall, just in a smaller area. That can actually make heat dissipation more centralized and more efficient (due to higher thermal gradient) so I think it's a solvable problem.
- Dylan16807 7y ago> IC design costs also continue to rise. The cost to design a 28nm planar device ranges from $10 million to $35 million, according to Gartner. In comparison, the cost to design a 7nm system-on-a-chip (SoC) ranges from $120 million to $420 million, according to Gartner. Is the comparison here a device with the same number of transistors, a device with the same area, or something else entirely? Because if that's the per-area cost, then the design cost per transistor has barely budged.