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Path to 2 nm May Not Be Worth It
- arnon 8y agoAll the more reason to go distributed and parallel, and embrace simpler architectures that can support this. We've gotten complacent. Software keeps getting faster, despite bad coding - just because of the improvements in hardware.
- chooseaname 8y agoWe've been complacent. Thus the old saying, "Intel giveth, Microsoft taketh away."[0] Engineers have known for a long time that we aren't as efficient as we could be. [0] Not attempting to beat up on either of those companies.
- overcast 8y agoI don't know, Windows 10 seems to be faster on even older hardware. Upgrading from 7 to 10 makes the machine feel MUCH more responsive. Seems to bring life back to the old machines around here.
- gameswithgo 8y agoMaybe you are just feeling a machine without bloat vs one with lots of bloat that has built up for 3rd party software? At least one aspect of windows10 design will add input latency, which is the forced vsync in the windowing system.
- overcast 8y agoNope, fresh installs of Windows 7 definitely not nearly as responsive. Thousands of machines a year, Windows 10 is by far the fastest.
- monocasa 8y agoNot sure why you're b eing downvoted. Windows 10 is the first release that Microsoft had really fully internalized the lessons learned from the whole Longhorn debacle. That is consumers aren't ever going to have 10Ghz processors.
- ghaff 8y agoWe've also just optimized for features, time to market, and programming approaches that don't require the most highly-skilled and trained developers. You can change all that of course (and we do for some applications/situations) but you don't get significantly more efficient code for free. It probably takes longer to write and a lot of current developers probably can't do it.
- gameswithgo 8y ago>We've also just optimized for features, time to market, and programming approaches that don't require the most highly-skilled and trained developers We think we have been optimizing for those things, but I don't know that we actually have. Does Ruby/Python really help you get to market faster than would similar languages with static typing and compilers or JITs? (Kotlin, C#, F#, Nim, etc) There is research that suggests not, certainly I don't think the effect is large if it even exists. Many people use TypeScript because they feel it is a productivity boon over Javascript. We might one day leverage that and use the static types to compile TypeScript more efficient WASM or something, win win situation.
- mrguyorama 8y agoIf you're looking for efficiency, wouldn't the actual win be to just use less javascript?
- gameswithgo 8y agoYes, but typescript is a great way to ease people into that, since it is a superset of javascript which could be leveraged to AOT compile more efficient code. Also it is a very nice language!
- jkabrg 8y agoIt's not clear what he's referring to. It could be garbage collection, libraries, frameworks, optimizing compilers... - Garbage collection make performance unpredictable because of collection spikes. - If you use a big library, you now have to load the library, which is an extra time-sink. - Likewise for frameworks. - Optimizing compilers optimize the 80% of our programs that don't need optimizing, and under-optimize the 20% that do. (This is DJB's argument.) That might be what he's saying. He didn't say anything about dynamic vs. static typing. Also, there's a counter-argument to this, that writing non-garbage-collected code might result in security bugs (to do with memory management). And security is a non-functional requirement that some might say is more important than speed. It's hard to judge though; there are loads of requiremenets in software dev, and it's hard to balance them.
- pacaro 8y agoOne irony of this expression is the role Intel played in making sure that as much of USB as possible had to go through the CPU
- agumonkey 8y agodo you have a list of things that are really in need of redesign ?
- ryanmarsh 8y agoI'm not a low level developer (whatever that means today). I've written a very minimal amount of production C. Everything else has been higher level languages. So I apologize in advance for my ignorance. Isn't the problem really memory bandwidth? Aren't most CPU cycles "wasted" on speculative execution while waiting on fetches from memory slower than CPU caches? Wouldn't a hardware model where all of the RAM (SRAM?) was on the CPU die (fabrication and DRAM clock speed aside) solve this problem and make everything an order of magnitude faster? What am I missing? Is this really the programmers fault? The CPU literally spends most of its time waiting on my instructions, not choking on them, so why is this my fault for being lazy?
- baybal2 8y ago>What am I missing? You are missing money... SRAM and wider data paths are expensive. You are totally right about that taking more logic into synchronous domain domain is an almost universal solution to getting more performance. The faster the chips become, the more IO gap becomes. Experienced MCU programmers know quite a number of algorithms that may run faster on "dumb" 100mhz MCUs than on a 20-cored Xeon, and are proud to show them off. Even when some of MCU cores may take like 6 cycles to do an arithmetic op, their strong side is that it will be taking them these 6 cycles to do that all and every time consistently, and that their memory runs synchronously. Say, in a 1000000 cycle loop, where every operation results in cache miss, Xeon will spend more time on a loop than a wimpy 100Mhz MCU that simply don't take any penalty on unpredictable, heavy on synchronous ops cope. Apple A11 is so fast for an ARM just because they choose the simplest, the surest, most direct, but also the most expensive way to scale performance: tons of SRAM and prefetch logic everywhere to reduce IO gap as much as possible.
- marcosdumay 8y agoMemory bandwidth is a problem. A large one. But saying that "most" CPU cycles are wasted to it is a huge overrate. I have read estimates that go as high as 1/3 of the CPU lost to it (sorry, no reference here), but even those were not usual.
- paulmd 8y ago20 MB of RAM should be enough for anybody! /s I was reading a thing a while back on here or Reddit where someone asked about an OS that ran entirely in cache, after all in principle a modern processor has more L3 than an original Unix minicomputer. Since many of the memory subsystems operate on the assumption that changes should be propagated to memory that you would still need to have RAM there even if you weren't really "using" it. There was a suggestion that since the bringup code begins entirely on-processor (before initializing RAM) that you could hack the Management Engine and keep running in that mode forever.
- cm2187 8y agoThe modern version being, "Intel giveth, javascript and python taketh away".
- wlesieutre 8y agoApple doing an optimization focused update with iOS 12 is a breath of fresh air. My iPad Pro 9.7" (one version old, came before the 10.5") drops frames in iOS 11's full screen blur transition animations. Before iOS 11 it was fine, but either the iOS team didn't test animations on anything but their brand new hardware, or they tested and didn't care if it ran smoothly. Having one of the OS's most frequent animations choke on anything but the brand newest GPU in the $650+ model? Not a great look, especially with Apple's reputation for making devices that last a while. Fingers crossed that iOS 12 fixes it.
- overcast 8y agoiOS 12 is indeed faster, but it seems to be at a cost to increased battery usage. From my understanding, CPU is ramped up to maximum performance mode when needed, like launching applications and other demanding tasks. Then dialed back down when not needed. It could be just the normal beta battery usage issues, but mine gets hit hard.
- gameswithgo 8y agogetting the work done as fast as possible then shutting down is usually the way to get the best battery life.
- overcast 8y agoI would agree, but doesn't seem to be the case here! This is also with a new(6 month) battery. It's either ramping up for much too long, or it's just normal beta battery usage.
- baybal2 8y agoNo, Power consumption scales roughly quadratically in relation to frequency. Modern cores all have features like power and frequency gating, performance counters - the stuff needed to allocate just enough of computing power to complete computations in time. This is very, very evident in things like music playback - a lot of intermittent io and computational spikes.
- jcranmer 8y ago> All the more reason to go distributed and parallel, and embrace simpler architectures that can support this. It's very easy to stamp out more ALUs on a chip than we can reasonably fill with data (and, arguably, we've already hit that point with consumer hardware). Improving parallelization nearly always comes at a cost to serial performance, and if you have code that requires a latency-sensitive, unparallelizable critical loop... well, you're basically saying "screw you."
- ansible 8y agoYou might be interested in the tech talks from Mill Computing: https://millcomputing.com/ https://millcomputing.com/ They're working on a new processor architecture, which is very interesting in many, many ways. And they're working on ways to parallelize existing code, in ways that can't really be done with conventional superscalar architectures.
- jcranmer 8y agoPeople keep bringing up the Mill processor in response to parallelization; I've been hearing about it for ~5 years now. And yet, where is it? I see lots of talk about its architecture, but there's no hard comparisons on things like "we get DGEMM at 2x the FLOPS/W of NVidia's latest GPU" or "we get 2x SPECCPU 2017 as Intel's latest processor."
- mechagodzilla 8y agoThat's because they don't have a real product, and they likely never will. For the most part, the ISA just needs to be 'good enough' to allow things like branch prediction, speculative execution, out-of-order execution, etc. You can do that with x86, ARM, POWER, whatever - the instruction set doesn't matter a whole lot, it's just how many/what type of transistors you can throw at it, and how hard you want to work on timing and power optimization. That's the biggest problem with Moore's law fizzling out - computer architecture isn't actually that hard, most of the work is just figuring out how to apply the extra transistors you're given. So no matter how specialized you get, you aren't going to get more than 1-2 generations of a chip out of a single semiconductor process, as there is only so much that clever architecture can accomplish.
- rootlocus 8y agoHerb Sutter wrote an article on this called "The Free Lunch is Over" in 2005, 13 years ago. http://www.gotw.ca/publications/concurrency-ddj.htm http://www.gotw.ca/publications/concurrency-ddj.htm
- ghaff 8y agoWhen it became clear around that time that processor frequency was tapped out and that multi-core was the future there was a lot of hand-wringing around parallel programing. There weren't the tools. There weren't the skills. Etc. For a variety of reasons, the issues turned out to be less than feared overall. But you were still getting more transistors at the time. You just had to use them in different ways.
- gameswithgo 8y ago>. Software keeps getting faster, despite bad coding Disagree. Much of it keeps getting slower.
- castlecrasher2 8y agoWebsites for sure. Load up HN compared to most shop or news sites, enormous difference.
- jcriddle4 8y agoHave you tried the latest fad? Serverless functions, so you take maybe a 128 to 512 MB of memory virtual machine and have it run a function that is maybe a few hundred lines of code? I double dare you to find something less efficient. Even better is the speed between machines isn't going to get that much faster as some jerk has declared the speed of light to be a constant so say hello to some fun latency issues. To top it off after you invest massive amounts in serverless functions, with all there lockin, you have no control over what Amazon, Microsoft or xxx are going to be charging you in 5 or 10 years. Particularly if the fad falls out of favor and these companies decide to wind the operations down.
- noir_lord 8y agoI agree with everything but your tone. I'm sure it solves problems they just aren't my problems. Which frankly applies to nearly everything AWS offers. I've seen people design for massive scaleout before they even have a final idea of the product. Frankly for the kind of systems I work on I have collosal vertical headroom before I even need to think about going lateral with scaling. I mean the largest database I deal with would fit into the RAM of a single mid-range 2018 server (192GB would do it). The most important database on our main work system will fit into the RAM on my Thinkpad with enough space to run an IDE and Vagrant (32GB of RAM in the laptop so high but insane).
- alayne 8y agoHave you seen the previous fad? Data centers full of idle servers.
- ghaff 8y agoThere are a lot of other levers to improve price/performance such as specialized hardware architectures. However CMOS process scaling has been a singularly powerful approach. I've read something like 3500X over the course of its lifetime. It's reasonable to ask whether any combination of other techniques can come close to that and what the effect is of price performance stagnating. You can always just add more computers in "the cloud" I suppose. But, at some level, increased functionality depends on better price performance.
- tomhoward 8y agoNote that this article was published over 5 months ago. Edit: This is not a topic of expertise for me so I have no idea whether the content is as valid now as it was when it was published. I was kinda hoping someone with expertise could inform us, given that it’s a fast-moving field.
- adamc 8y agoI doubt that the conclusions have changed.
- Symmetry 8y agoThe march of faster and faster transistors seems to be headed for an interregnum until some new technology can replace CMOS. Price per compute might still continue to fall though. I hope that we'll see an era of more architectural diversity coming up as the end of the march of nodes mean that a design can take longer to pay off and still be economical.
- ghaff 8y ago>an era of more architectural diversity We're already seeing this in machine learning. I used to follow the processor space fairly closely and I'd see various companies come out with designs that were specialized for some workload or other. The problem was that you could instead wait for a couple years and x86 would be just as fast. You also have some other things going on like open source software, centralized computing in clouds, etc. that make having hardware that's optimized for some specific workload much more tenable.
- baybal2 8y ago>The problem was that you could instead wait for a couple years and x86 would be just as fast. This still holds for the majority of users. Only tier 1 dotcoms can run stuff on GPUs economically. For everybody else, just getting many times, possibly few magnitudes, more commodity x86 machine time still makes sense. I always remember the saying of my ops unit head once I worked in an advertising network. It was something to the meaning of: "a new coder like you who can find a fancy algo to do thing A and B faster pays off in two years, but a 10 new servers will pay off in just 2 month" And I am still convinced that fabs will continue mercilessly squeezing CMOS till the last drop of blood for at least a decade. There are tons and tons of avenues to make cells smaller, cooler, and more performant that don't involve further process down scaling or switching to a next gen semiconductor.
- edraferi 8y ago> Only tier 1 dotcoms can run stuff on GPUs economically. For everybody else, just getting many times, possibly few magnitudes, more commodity x86 machine time still makes sense. Disagree. Anybody running appreciable ML workloads buys and racks their own GPUs.
- amelius 8y agoOfftopic, are 3D chips still being researched? I mean not two dies glued together but true multilevel semiconductors. What are the biggest challenges (I guess heat is one, and semiconductor lattice another), and how big would the advantages be?
- gameswithgo 8y agothey are already multiple levels. If you are imagining something like a cube, heat dissipation is a big problem there.
- ashleyn 8y agoNot insurmountable I would gather. Probably just need microscale heat pipes. Then again, I dunno physics well enough to know this won't work.
- jmcqk6 8y agoI just learned about microfluidics[1] the other day, so now I'm seeing possible applications everywhere. I wonder if this is one such possible application. [1]https://en.wikipedia.org/wiki/Microfluidics https://en.wikipedia.org/wiki/Microfluidics
- bwbw223 8y agoHow about a sphere-ish thing, then? Or a tube-like cylindrical thing?
- contravariant 8y agoYou need more surface area not less. I suppose a long tube might work, but that'd be a weird shape to work with.
- m1573rp34130dy 8y agothe whole idea of a flat linear trace may be a dead end... high frequencies dont propagate very well through the cross sectional area of a conductor...skin effect and antenna effect dictate many of the design constraints regarding width thickness proximity and linear segment length...we may begin to see hollow duct waveguides required to manage propagation of gigahertz even terahertz frequency electron waves if we dont go full out photonic...im hoping to see carbon/ graphene nanotube die production facilities, even if only experimental for the remainder of my lifetime...lets catch the wave and promote to the next level...
- LeanderK 8y agoWell, there has to be an end to exponentially growth somewhere...but I remeber that being preached that Moores Law is ending for years. I recently saw old slides from a professor at my uni from the 2000ers containing the "the end of exponential growth is near!"-like messages. So I am not sure what to believe.
- cultus 8y agoMoore's law as far as serial performance ended years ago. This means exponential growth has effectively ended for most tasks because of Amhdahl's law.
- gameswithgo 8y agoMoore's law did stop being true right around ~2006. And if you look at overall CPU and memory performance rather than transistor density the story is worse. You haven't been able to count on the computer being twice as fast very soon in a long time.
- takeda 8y agoWhat's nice (at least I like it) is that once performance slowed down, so did software requirements. Developers try a bit harder to optimize their code.
- Symmetry 8y agoSort of. Moore's law has meant a lot of things that were all tied together with transistor scaling back when voltage didn't need to be scaled down with each new node to fight leakage. But now that leakage is a major concern a lot of what would have been the old gains of shrinking a transistor go away. There are gains but they're a lot smaller than they used to be. But the oldest sense of Moore's law of doubling the transistors you can economically fit on a piece of silicon is very much with us. The doubling period has gone back to the original 2 years rather than the 18 months we were able to achieve for a while but it's still happening.
- ksec 8y agoWhat "exactly" is the reason that road to 2nm may not be worth it? I don't see the article makes any answer to it. Qualcomm are comparing 10nm and 7nm, and those figure are not as high as a generation node should be, and that is perfectly fine because 10nm from TSMC are half node. They should be comparing 14/12nm with 7nm, and there are multiple iteration of 7nm. Does it scale as perfectly as before? No. It isn't about the complexity and design rules. It is about all about cost, and it only means chips are going to be more expensive going forward and only few companies will be able to afford it, but there are nothing on the roadmap suggest 2nm isn't worth it. This article reminds me of the old days 10 to 15 years ago when they keep saying the end of Moores law.
- exmadscientist 8y agoWhat's different now is that everything is running out of steam, not just one component of the process. Lithography is getting exponentially more complicated: the cost of a mask set for a 7nm-class process is obscene. Materials are getting exotic: the serious discussion around use of ruthenium, which is notoriously difficult to work with at nanoscale, tells you how desperate people are getting. Even the fundamental structures are getting bizarre: FinFETs got us to ~5nm, but nanosheet or gate-all-around structures are going to be necessary to go further. And all of this exoticism is expensive, so chips just aren't getting cheaper to make like they used to. Plus reliability is going to hell and costs are out of control.... Basically, the stars are aligning to spell the end of traditional CMOS scaling. 7nm nodes are in early production now; 5nm is on the way; 3nm is likely to happen; 2nm may or may not depending on the economics; 1nm is unlikely but you never know; and sub-nm CMOS nodes are probably just not going to happen. (Don't confuse actual nodes with what happens when marketing gets involved. Some twat sticking a "2nm" label on a 20nm-class process doesn't actually make it any better!) This isn't to say that semiconductors will stop improving, just that it sure won't be classic CMOS any more. One under-explored area I think we're going to see a lot more of is backfill of older processes. Very few things actually need the latest and greatest digital process: main processors (CPUs, APUs, GPUs) are about it. I think there's plenty of room for improving cost on older processes to make them more widely deployable. To some extent we're seeing that now with SOI processes like 22FDX, but I think that trend will continue. (Unfortunately, there's a lot of stuff that just doesn't shrink, period: some analog stuff, all HV I/O cells, and just about all power management.) So the potential upsides aren't universal, but I think there's a big market out there for stuff that can benefit from smaller processes but can't afford the obscene cost of a multipatterning mask set.
- hinkley 8y agoOne of the reasons we go smaller is to decrease worst case signalling delays between components. When do we start using optical interconnects?
- mmt 8y agoIs the speed of light for light-in-some-substrate sufficiently faster than the speed of light for electrical charge? Is there any speed penalty for converting between the two?
- m1573rp34130dy 8y agothe speed of light is always the speed of light, you have to observe at sufficiently small scale to make this observation. light in a medium travels between obstacles in a less than linear trajectory thus has an "apparent" average velocity. conversion from photonic to electronic can be very fast such as photonic emission during valence electron demotion, but in a practical case a junction has a latency and a fuzziness due to thermalnoise and quantum uncertainty...that is where the penalties will occur... conceptually there are 2 ends of a stick, does light actually move, or does light stand still while spacetime unfolds at "the speed of light"
- mmt 8y agoSo, for a lay person, what's the summary? Does using optics as an interconnect in an otherwise electrical system add noticeable latency?
- m1573rp34130dy 8y agoyou are only as fast as your slowest segment... if you are moving single bits there is no problem... if you are using pulse width modulation or some other method of signal fidelity to stream packets then you will have to explore latency issues... if you are talking about single photons transverting to single electrons...you will have issue due to quantum interference... ...optocoupler latency is important and must be considered in your design, if you are working at circuit board level... im wondering just what your implementation is, are you talking "audiophile" equipment, are you talking digital data transmission... is it a human eye/ear noticing latency or is it an electronic component, that will consequently influence the smooth operation of the circuit?
- mikeymop 8y agoWhat about building up? It seems most designs are relatively two dimensional. AMD's High Bandwidth memory and Samsungs high density NAND seem to open up another axis to continue doubling transistor count in a given area. It'd be interesting to see things be engineered this way as devices are starting to become too thin to be comfortable.
- MrEldritch 8y agoThe fundamental problem with three-dimensional logic is heat. Getting the heat out of the chips so they don't melt is already one of the largest performance bottlenecks in the entire industry; putting more layers on top where they block heat flow out of the interior layers makes the cooling problem intractable. 3D memory is a lot more tractable because it doesn't have to do nearly as much as a CPU. You don't typically worry about cooling your RAM. There is a type of logic efficient enough that we can think seriously about monolithic 3D integration; superconducting Josephson junctions at liquid-helium temperatures are really, really efficient. There's some hopes that spintronics may one day give us sufficiently efficient switches at room temperature. But we've wanted to integrate our chips in 3D for decades - transistor scaling aside, routing latency adds a lot of overhead and the length of the wires you need only gets worse the more transistors you need to connect with them. (It's an n^2.something scaling, IIRC). All else being equal, 3D integration of the exact same number of transistors as a 2D CPU would result in a major performance boost all on its own, by making the routing much more straightforward and direct. The reason we haven't done it isn't because we haven't thought of it, or haven't tried to do it - it's because we can't. (Also, manufacturing a 3D chip is really tricky)
- marcosdumay 8y agoThe largest practical problem with going 3D is how do you cool the chip? But then, what is really the gain? You will be trading a larger number of chips per die for a proportionally more expensive process. Besides some faster communication (may be great for L1 cache), I can only see it adding problems.
- DesiLurker 8y agoIMO this will be the final forcing function for silicon photonics. ultimately if you cannot scale on-die you have to scale off-die. plus this takes away any further scaling concerns about on/off board components. lastly this will have major implications for processor architecture because memory access latency is quite huge and execution is often stalled for memory access. if you have any doubts about that just look at the amount of area dedicated to caches. AFAIK Intel & luxtera are the two main leaders in silicon photonics so I wouldn't count intel out yet.