11 ms·
RISC-V based 64-bit quad-core application processor
- rightos 9y agoVery interesting, any information about a target price range?
- zitterbewegung 9y agoDoesn't look like it but I would sign up on the bottom to get more info. (aside it should be on the top of the page)
- opencl 9y agoThis is an IP core rather than an actual SoC so the pricing will obviously depend on what else gets packaged with it, but based on the core+caches area of 0.538mm^2 on 28nm it should be competitive with the Cortex A7/A53/A35. As seen in Allwinner A64, Raspberry Pi, etc. It does say 2MB of L2 cache whereas most quad A53 SoCs I've seen have 512KB so the cost is probably going to be a bit higher from that. But full SoCs are likely going to be in the $5-$10 range.
- petra 9y agoThe raw cost of the coreplex's silicon is probably ~7 cents. of course there's extra stuff that goes into a soc, but why do you assume it will go from 7 cents to $5-$10 ? is it because the cost of the A53 etc is insignificant ?
- pdq 9y agoYou have to take into account the end product, not just raw silicon cost. There are costs in SoC packaging, wire bonding, testing, yield loss, warehousing, distribution, R&D, and profit.
- pjc50 9y agoSince when have the silicon costs been the slightest bit relevant to IC pricing? It's all about volume and recouping R&D costs and other NRE.
- monocasa 9y agoYeah, but this core is open source, which significantly reduces the NRE costs for most integrators.
- pjc50 9y agoIt looks like (although not 100% clear) it's available as hard IP, which means they've done the layout, but the very expensive mask NRE remains. (They have a plan for an actual SOC but aren't shipping yet: https://www.sifive.com/documentation/freedom-soc/freedom-u500-platform-brief/ https://www.sifive.com/documentation/freedom-soc/freedom-u50... )
- opencl 9y agoThe RISC-V ISA is free (i.e. you can design your own core without paying royalties to a company like ARM, which is what SiFive has done here) but this is a normal paid-for IP core. They do have some SoCs with a "free and open platform specification" but there's no public repo to download their Verilog code from. If you want an actual open source RISC-V core, see: https://github.com/lowRISC/lowrisc-chip https://github.com/lowRISC/lowrisc-chip
- monocasa 9y agoThe source here isn't their core? https://github.com/sifive/freedom https://github.com/sifive/freedom
- opencl 9y agoThat code seems to be for an FPGA devkit for their SoC but using an entirely different CPU core, the Berkeley Rocket Chip. They're selling coreplex licenses for several hundred thousand dollars (not the one in the linked product page, it isn't for sale yet): https://dev.sifive.com/coreplex-risc-v-ip/buy/rtl/e51_coreplex/configure/ https://dev.sifive.com/coreplex-risc-v-ip/buy/rtl/e51_corepl...
- simonh 9y agoI suppose the money for the wages of all the people working at the billion dollar silicon chip fab plant has to come from somewhere.
- imtringued 9y agoBecause it will cost you 10 million dollars+ to produce your first chip. Every chip after that costs you 7 cents.
- mtgx 9y ago1.7 DMIPS/MHz seems to put it in the range of Cortex A5, maybe Cortex A7. But it also targets significantly higher clock speeds of 1.5GHz, so it may be faster than Cortex A7 in the real world. Probably not faster than A53/A35, but it should be close enough. Plus it has some additional features. https://www.cnx-software.com/2015/04/09/relative-performance-of-arm-cortex-a-32-bit-and-64-bit-cores/ https://www.cnx-software.com/2015/04/09/relative-performance... What may hurt it more in the market is the name. Most companies seem to underestimate its importance. U54-MC Coreplex doesn't exactly roll off the tongue...That means it's that much easier to ignore and forget about it. Hopefully whatever SoC will use it will have a better name.
- makapuf 9y agoWell the esp8266 80386, x86-64 or 741 chips didn't perform too bad either. ( I know x86 64 was an arch and not a chip)
- ant6n 9y agou54 rolls off the tongue. Sounds like a u-boot, too. With a night club.
- userbinator 9y agoTo compare with x86, 1.7 DMIPS/MHz is slightly less than the original Pentium (P5) at 1.88 DMIPS/MHz, and well behind the Pentium Pro (P6) at 2.7 DMIPS/MHz. Later x86 microarchitectures are vastly more efficient, with modern i7s achieving closer to 10 DMIPs/MHz. https://en.wikipedia.org/wiki/Million_instructions_per_second https://en.wikipedia.org/wiki/Million_instructions_per_secon...
- jabl 9y agoIsn't this pretty good then? P5-level performance/MHz from a pretty simple in-order scalar processor. And it clocks at 1.5GHz whereas the P5 topped out at around 200MHz. Though I suppose if you'd manufacture a (slightly tweaked) P5 on a modern process you'd reach similar clock speeds too...
- angrygoat 9y agoI'm quite excited about Risc-V as a platform - particularly security and trust-wise. It's great to see that we'll be getting competitive CPUs soon. Open hardware, implementing an open architecture, which can run open source software with reproducible builds. A huge win when we're facing pervasive surveillance hard-wired into current commodity systems.
- monocasa 9y ago> particularly security and trust-wise Towards that end, has there been work on a TileLink IOMMU yet?
- sweden 9y agoOpen hardware? Open architecture? SiFive's solution is neither of those.
- sigjuice 9y agoI wish I could share your optimism :/ Nothing stops makers of RISC-V SoCs from adding their own Intel ME equivalents. Also, the CPU is just a small part of a computer, so "RISC-V" doesn't automatically translate to "open hardware" or "open architecture".
- microcolonel 9y ago> Also, the CPU is just a small part of a computer, so "RISC-V" doesn't automatically translate to "open hardware" or "open architecture". It is a prerequisite to it though. update: Also, they already have something acting in the role of the ME on this machine, marked E51 on the chart. I don't think it does the high level application type stuff that the ME does, but I would think it handles power management and other core duties of the ME.
- saosebastiao 9y agoAFACT, the only non-incremental innovations in CPU architecture these days is open source commoditization (the RISC-V approach) and taking VLIW to the extreme (the Mill Computing approach). Maybe we've hit diminishing returns, but both of those ideas still seem super promising to me. The baffling thing is that we've got VC money coming out of our ears. They're funding unicorns with no hope of returns and funding every single uber-for-x idea under the sun. And yet it seems like both of these approaches have received almost zero funding in comparison. How is it that Mill Computing and SiFive (or any other RISC-V commercialization company), have not received billions of dolllars in venture capital yet?
- baobrien 9y agoI don't know much about SiFive, but I have heard that Mill Computing is bootstrapped and doesn't want to take any VC funding.
- nerdponx 9y agoWhat's the value proposition though?
- CalChris 9y agoSiFive is Berkeley is funding.
- wmf 9y agoVCs invest in monopolies, not commoditization.
- microcolonel 9y agoCustomers buy into commodities when they are competitive with the monopolies. VCs invest in ventures, and if those ventures are making money I don't think the they care what kind of market you're competing in.
- e12e 9y ago> AFACT, the only non-incremental innovations in CPU architecture these days is open source commoditization (the RISC-V approach) and taking VLIW to the extreme (the Mill Computing approach). I'm still fascinated by the approach of Green Arrays; 144 tiny (forth) cores that together can lift about as much as a "small" cpu, but can also idle at low power with only a few cores active... But That might be "too new"? http://www.greenarraychips.com/ http://www.greenarraychips.com/
- gioele 9y ago> U54-MC Coreplex IP is the world’s first RISC-V based 64-bit quad-core application processor, supporting full-featured operating systems such as Linux. Isn't the (still in draft state) Privileged ISA needed to implement a UNIX-like OS such as Linux?
- _chris_ 9y agoThe current version (v1.10) should be forward-compatible, and I believe is expected to be fully ratified in the next two months. There has been very little churn on it for a while now. [Edit: RISC-V Linux is being upstreamed, and rocket-chip has been running Linux for years.]
- Timothycquinn 9y agoLooks awesome. Seems like this hardware may be the start of a pivot back towards RISC for general computing. Anybody have an idea if work has started on build of OpenBSD or FreeBSD for Risc-v? Would make an excellent chip for building super secure network edge devices or FreeNAS box.
- userbinator 9y agoSeems like this hardware may be the start of a pivot back towards RISC for general computing. I doubt it. RISC-V will probably be seen more as "truly free and open MIPS", and maybe eventually start growing CISC-ish extensions --- they will have to if they want to become/remain competitive with other more popular architectures. Even ARM has become more CISC-y with the introduction of more special-purpose instructions. Would make an excellent chip for building super secure network edge devices or FreeNAS box. That is where I think RISC-V will find a lot of adoption --- since many low-end routers and other network devices already use MIPS (and have barely adequate performance.)
- microcolonel 9y agoI don't think there's really any reason to think it won't take off in the datacenter, on Chromebooks, on Android devices, and network/embedded equipment as you mention. Each of these will have a different timeline, but these days there are major markets which are more agnostic to ISA than they were five years ago. The inherent commodity nature of designs and silicon based on a royalty-free ISA will drive down prices to the limits of design and material process, which will drive adoption.
- nickik 9y agoIf the processor adds more functionality, it should get more instruction, that's why it is extendable. However there is no reason to add specialized instructions for things that can be expressed at a lower level, and that would be CISC. The data and test already done by clearly show that the core premise of the advantages of risc is true. The chips are less complex because of the feature set and use less area and less power.
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- phkahler 9y agoThe EE-times article is better IMHO. They hint at some SiFive customers. There's also a quote about embedded risc-v taking off already - if so I think we should see these appearing next year. https://www.eetimes.com/document.asp?doc_id=1332398 https://www.eetimes.com/document.asp?doc_id=1332398
- snvzz 9y agoDid I miss the privileged ISA specification passing?